80C186EC/80C188EC Microprocessor User's Manual

PERIPHERAL CONTROL BLOCK
Register Name:
Register Mnemonic:
Register Function:
PCB Relocation Register
RELREG
Relocates the PCB within memory or I/O space.
15 0
E
T
M
E
M
R
1
9
R
1
8
R
1
7
R
1
6
R
1
5
R
1
4
R
1
3
R
1
2
R
1
1
R
1
0
R
9
R
8
A1263-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
ET Escape Trap 0 The ET bit controls access to the math coprocessor.
If ET is set, the CPU will trap (resulting in
a Type 7 interrupt) when an ESC instruction is
executed.
NOTE: The 8-bit bus version of the device
automatically traps an ESC opcode to the Type 7
interrupt, regardless of the state of the ET bit.
MEM Memory I/O 0 The MEM bit specifies the PCB location. Set
MEM to locate the PCB in memory space, or
clear it to locate the PCB in I/O space.
R19:8 PCB Base
Address
Upper Bits
NOTE:
0FFH
R19:8 define the upper address bits of the PCB
base address. All lower bits are zero. R19:16 are
ignored when the PCB is mapped to I/O space.
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 4-1. PCB Relocation Register
Table 4-1. Peripheral Control Block
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
Function
PCB
Offset
Function
00H MPICP0 40H T2CNT 80H GCS0ST C0H D0SRCL
02H MPICP1 42H T2CMPA 82H GCS0SP C2H D0SRCH
4-2