80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
The Interrupt Request Register bits feed into the Priority Resolver. The Priority Resolver decides
which of the pending interrupt requests is the highest priority based on the programmed operating
mode. The Priority Resolver controls the interrupt request line to the CPU. The Priority Resolver
has a default priority scheme that places IR0 as the highest priority and IR7 as the lowest priority.
The priority can be modified through software. (See “The Priority Resolver and Priority Resolution”
on page 8-10.)
When an interrupt is acknowledged, an In-Service Register bit is set for that specific interrupt
source. In some operating modes, the Priority Resolver looks at the In-Service Register in order
to make its decision. In Fully Nested Mode, for example, the Priority Resolver needs to know
whether a higher-priority interrupt is already in service before it interrupts the CPU. An interrupt
handler must explicitly clear the In-Service bit for its interrupt before returning control to the
main task. (See “The In-Service Register” on page 8-12.)
The Interrupt Mask Register contains one bit for each interrupt request (IR) line. The Interrupt
Mask Register allows the selective disabling of individual interrupt request sources. (See “Masking
Interrupts” on page 8-14.)
An interrupt request line is also referred to as an interrupt level. For example, an interrupt on IR
line 7 is also called a “level 7 interrupt.” Figure 8-4 shows a simplified logic diagram for the circuitry
for one IR line (or priority cell).
Multiple 8259A modules can be connected together to expand the interrupt processing capability
beyond eight levels. (See “Cascading 8259As” on page 8-14.) The Cascade Buffer/Comparator
is used only when the 8259A module is programmed for cascade mode. During an INTA cycle,
the Cascade Buffer of the master 8259A drives the address of the slave 8259A module that is being
acknowledged. Each slave 8259A module uses the Cascade Comparator to determine whether
it is the addressed slave.
8.3.1 A Typical Interrupt Sequence Using the 8259A Module
The function of the 8259A module is best illustrated by an example. For this example we assume
the simplest of 8259A module configurations: a single master with the default fixed priority and
programmed for Fully Nested Mode. The initial conditions are as follows:
• the 8259A has just been initialized
• there are no pending interrupts
• all interrupts are unmasked
• the IR inputs are programmed as edge-sensitive lines
8-6