80C186EC/80C188EC Microprocessor User's Manual

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Serial Communications Unit 11
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
Page 278 and 279: TIMER/COUNTER UNIT Timer 0 Serviced
Page 280 and 281: TIMER/COUNTER UNIT 9.3.2 Synchroniz
Page 282 and 283: TIMER/COUNTER UNIT lib_80186 segmen
Page 284 and 285: TIMER/COUNTER UNIT $mod186 name exa
Page 286: TIMER/COUNTER UNIT _CMPB equ word p
Page 290 and 291: CHAPTER 10 DIRECT MEMORY ACCESS UNI
Page 292 and 293: DIRECT MEMORY ACCESS UNIT 10.1.1.1
Page 298 and 299: DIRECT MEMORY ACCESS UNIT The Chip-
Page 300 and 301: DIRECT MEMORY ACCESS UNIT Both Requ
Page 304 and 305: DIRECT MEMORY ACCESS UNIT Channel a
Page 306 and 307: DIRECT MEMORY ACCESS UNIT Register
Page 312 and 313: DIRECT MEMORY ACCESS UNIT When inte
Page 314 and 315: DIRECT MEMORY ACCESS UNIT The trans
Page 316 and 317: DIRECT MEMORY ACCESS UNIT 10.2.4 Su
Page 318 and 319: DIRECT MEMORY ACCESS UNIT 10.3.1 DR
Page 320 and 321: DIRECT MEMORY ACCESS UNIT $MOD186 n
Page 322 and 323: DIRECT MEMORY ACCESS UNIT SECTORS M
Page 324 and 325: DIRECT MEMORY ACCESS UNIT XOR AX, A
Page 326 and 327: DIRECT MEMORY ACCESS UNIT $mod186 n
Page 330 and 331: CHAPTER 11 SERIAL COMMUNICATIONS UN
Page 332 and 333: SERIAL COMMUNICATIONS UNIT Receptio
Page 334 and 335: SERIAL COMMUNICATIONS UNIT SxTBUF F
Page 336 and 337: SERIAL COMMUNICATIONS UNIT TXD/ RXD
Page 338 and 339: SERIAL COMMUNICATIONS UNIT 11.2 PRO
Page 340 and 341: SERIAL COMMUNICATIONS UNIT Register
Page 342 and 343: SERIAL COMMUNICATIONS UNIT Due to i
Page 348 and 349: SERIAL COMMUNICATIONS UNIT The CPU
Page 350 and 351: SERIAL COMMUNICATIONS UNIT 11.3.3.2
Page 352 and 353: SERIAL COMMUNICATIONS UNIT 11.5.2 M
Page 354 and 355: SERIAL COMMUNICATIONS UNIT MASTER 1
Page 356 and 357: SERIAL COMMUNICATIONS UNIT $mod186
Page 358 and 359: SERIAL COMMUNICATIONS UNIT $mod186
Page 360 and 361: SERIAL COMMUNICATIONS UNIT cmp al,
Page 362: Watchdog Timer Unit 12
Page 365 and 366: WATCHDOG TIMER UNIT Figure 12-2 sho
Page 367 and 368: WATCHDOG TIMER UNIT 12.2.2 Watchdog
Page 369 and 370: WATCHDOG TIMER UNIT 12.3 USING THE
Page 371 and 372: WATCHDOG TIMER UNIT wdt_data segmen
Page 373 and 374: WATCHDOG TIMER UNIT Register Name:
Page 375 and 376: WATCHDOG TIMER UNIT Register Name:
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Input/Output Ports 13
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS 13.1.4.1 Port 1
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS 13.3 PROGRAMMING
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CHAPTER 14 MATH COPROCESSING The 80
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MATH COPROCESSING 14.3.1.1 Data Tra
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MATH COPROCESSING 14.3.1.3 Comparis
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MATH COPROCESSING 14.3.2 80C187 Dat
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING Bus cycles involv
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MATH COPROCESSING 14.4.4 Exception
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MATH COPROCESSING $mod186 name exam
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ONCE Mode 15
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80C186 Instruction Set Additions an
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX B INPUT SYNCHRONIZATION Ma
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Instruction Set Descriptions C
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS INC IN
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INSTRUCTION SET DESCRIPTIONS OR OUT
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Instruction Set Opcodes and Clock C
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INSTRUCTION SET OPCODES AND CLOCK C
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INDEX 80C187 Math Coprocessor, 14-2
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INDEX registers, 6-5-6-15 system di
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INDEX port 2, 13-6 port 3, 13-7 pro
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INDEX P Packed BCD, defined, 2-37 P
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INDEX SCU asynchronous mode, 11-21-
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80C186EC/80C188EC Microprocessor User's Manual

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