80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
4. Fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table
and begins executing from that point.
8.2 INTERRUPT PRIORITY AND NESTING
The priority of certain interrupts may change during program execution, or the program may wish
to ignore some interrupt sources entirely. The interrupt controller must offer the capability of
modifying interrupt priorities on the fly and must allow for the masking of individual interrupt
sources. The priority scheme used by a particular application is known as the interrupt structure.
In many systems, it is possible that an interrupt handler may itself be interrupted by another device.
This situation is known as interrupt nesting. Typically the system would want only higherpriority
interrupt sources to interrupt a handler in process. For example, you would want your
hard disk drive handler to be interrupted by an impending shut-down interrupt but not by a keyboard
keystroke. Systems that allow only higher-priority interrupts to preempt handlers currently
in service are called fully nested. Fully nested is the default interrupt structure used by the 8259A
module.
There are times when it is appropriate to use an interrupt structure other than fully nested. For
example, during execution of an interrupt handler it may be necessary to temporarily enable interrupts
from a lower-priority source. The 8259A has several alternate modes that allow modifications
to the fully nested structure.
It is important to define the interrupt structure early in the system design process. Interrupt priority
is controlled by both the hardware and software design. It may not be possible to change the
interrupt structure “in software” if the hardware is incorrectly designed. When developing an interrupt
structure for your system, consider the effects of software interrupts, traps, exceptions and
non-maskable hardware interrupts.
8.3 OVERVIEW OF THE 8259A ARCHITECTURE
The 8259A Programmable Interrupt Controller was first introduced as a peripheral chip for 8085
and 8086/8088 microcomputer systems. The 8259A architecture has since been reimplemented
as a CMOS module for inclusion in more highly integrated devices.
The 8259A module (Figure 8-3) is divided into several functional blocks. The data bus buffer and
read/write logic constitute the interface between the 8259A module and the CPU. The 8259A
module’s internal control registers are accessed through this interface. This block drives the interrupt
vector type on the bus during an INTA cycle.
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