80C186EC/80C188EC Microprocessor User's Manual

CONTENTS
FIGURES
Figure
Page
6-6 STOP Register Definition .............................................................................................6-8
6-7 Wait State and Ready Control Functions ...................................................................6-12
6-8 Overlapping Chip-Selects...........................................................................................6-13
6-9 Using Chip-Selects During HOLD ..............................................................................6-15
6-10 Typical System ...........................................................................................................6-16
6-11 Guarded Memory Detector.........................................................................................6-20
7-1 Refresh Control Unit Block Diagram.............................................................................7-1
7-2 Refresh Control Unit Operation Flow Chart..................................................................7-3
7-3 Refresh Address Formation..........................................................................................7-4
7-4 Suggested DRAM Control Signal Timing Relationships...............................................7-6
7-5 Formula for Calculating Refresh Interval for RFTIME Register....................................7-7
7-6 Refresh Base Address Register ...................................................................................7-8
7-7 Refresh Clock Interval Register....................................................................................7-9
7-8 Refresh Control Register............................................................................................7-10
7-9 Refresh Address Register ..........................................................................................7-11
7-10 Regaining Bus Control to Run a DRAM Refresh Bus Cycle......................................7-14
8-1 Interrupt Control Unit Block Diagram............................................................................8-2
8-2 Interrupt Acknowledge Cycle........................................................................................8-3
8-3 8259A Module Block Diagram......................................................................................8-5
8-4 Priority Cell ...................................................................................................................8-7
8-5 Spurious Interrupts .....................................................................................................8-10
8-6 Default Priority............................................................................................................8-11
8-7 Specific Rotation ........................................................................................................8-11
8-8 Automatic Rotation .....................................................................................................8-12
8-9 Typical Cascade Connection......................................................................................8-15
8-10 Spurious Interrupts in a Cascaded System ................................................................8-18
8-11 8259A Module Initialization Sequence .......................................................................8-23
8-12 ICW1 Register ............................................................................................................8-24
8-13 ICW2 Register ............................................................................................................8-25
8-14 ICW3 Register — Master Cascade Configuration......................................................8-27
8-15 ICW3 Register — Slave ID.........................................................................................8-28
8-16 ICW4 Register ............................................................................................................8-29
8-17 OCW1 — Interrupt Mask Register..............................................................................8-31
8-18 OCW2 Register ..........................................................................................................8-32
8-19 OCW3 Register ..........................................................................................................8-34
8-20 Poll Status Byte ..........................................................................................................8-35
8-21 Interrupt Request Latch Register Function.................................................................8-37
8-22 Default Slave 8259 Module Priority ............................................................................8-38
8-23 Multiplexed Interrupt Requests...................................................................................8-39
8-24 DMA Interrupt Request Latch Register.......................................................................8-40
8-25 Serial Communications Interrupt Request Latch Register..........................................8-41
8-26 Timer Interrupt Request Latch Register .....................................................................8-42
8-27 Interrupt Resolution Time ...........................................................................................8-43
8-28 Resetting the Edge Detection Circuit..........................................................................8-44
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