80C186EC/80C188EC Microprocessor User's Manual

More documents

Recommendations

Info

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.6 Processor Control Instructions Processor control instructions (see Table 2-11) allow programs to control various CPU functions. Seven of these instructions update flags, four of them are used to synchronize the microprocessor with external events, and the remaining instruction causes the CPU to do nothing. Except for flag operations, processor control instructions do not affect the flags. Table 2-11. Processor Control Instructions Flag Operations STC CLC CMC STD CLD STI CLI Set Carry flag Clear Carry flag Complement Carry flag Set Direction flag Clear Direction flag Set Interrupt Enable flag Clear Interrupt Enable flag External Synchronization HLT WAIT ESC LOCK Halt until interrupt or reset Wait for TEST pin active Escape to external processor Lock bus during next instruction No Operation NOP No operation 2.2.2 Addressing Modes The 80C186 Modular Core family members access instruction operands in several ways. Operands can be contained either in registers, in the instruction itself, in memory or at I/O ports. Addresses of memory and I/O port operands can be calculated in many ways. These addressing modes greatly extend the flexibility and convenience of the instruction set. The following paragraphs briefly describe register and immediate modes of operand addressing. A detailed description of the memory and I/O addressing modes is also provided. 2.2.2.1 Register and Immediate Operand Addressing Modes Usually, the fastest, most compact operand addressing forms specify only register operands. This is because the register operand addresses are encoded in instructions in just a few bits and no bus cycles are run (the operation occurs within the CPU). Registers can serve as source operands, destination operands, or both. 2-27
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Immediate operands are constant data contained in an instruction. Immediate data can be either 8 or 16 bits in length. Immediate operands are available directly from the instruction queue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an immediate operand. Immediate operands can be only source operands and must have a constant value. 2.2.2.2 Memory Addressing Modes Although the Execution Unit has direct access to register and immediate operands, memory operands must be transferred to and from the CPU over the bus. When the Execution Unit needs to read or write a memory operand, it must pass an offset value to the Bus Interface Unit. The Bus Interface Unit adds the offset to the shifted contents of a segment register, producing a 20-bit physical address. One or more bus cycles are then run to access the operand. The offset that the Execution Unit calculates for memory operand is called the operand’s Effective Address (EA). This address is an unsigned 16-bit number that expresses the operand’s distance, in bytes, from the beginning of the segment in which it resides. The Execution Unit can calculate the effective address in several ways. Information encoded in the second byte of the instruction tells the Execution Unit how to calculate the effective address of each memory operand. A compiler or assembler derives this information from the instruction written by the programmer. Assembly language programmers have access to all addressing modes. The Execution Unit calculates the Effective Address by summing a displacement, the contents of a base register and the contents of an index register (see Figure 2-12). Any combination of these can be present in a given instruction. This allows a variety of memory addressing modes. 2-28
Page 1 and 2:
80C186EC/80C188EC Microprocessor Us
Page 3 and 4:
Information in this document is pro
Page 5 and 6:
CONTENTS 2.3 INTERRUPTS AND EXCEPTI
Page 7 and 8:
CONTENTS 6.4 PROGRAMMING...........
Page 9 and 10: CONTENTS CHAPTER 9 TIMER/COUNTER UN
Page 11 and 12: CONTENTS 11.4 SERIAL COMMUNICATIONS
Page 13 and 14: CONTENTS FIGURES Figure Page 2-1 Si
Page 15 and 16: CONTENTS FIGURES Figure Page 6-6 ST
Page 17 and 18: CONTENTS FIGURES Figure Page 11-18
Page 19 and 20: CONTENTS Table TABLES Page C-1 Inst
Page 22: Introduction 1
Page 25 and 26: INTRODUCTION The 80C186 Modular Cor
Page 27 and 28: INTRODUCTION Table 1-2. Related Doc
Page 29 and 30: INTRODUCTION 1.3.2.1 How to Find Ap
Page 32: Overview of the 80C186 Family Archi
Page 35 and 36: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 59: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 84: Bus Interface Unit 3
Page 87 and 88: BUS INTERFACE UNIT Physical Impleme
Page 89 and 90: BUS INTERFACE UNIT (X + 1) (X) A19:
Page 91 and 92: BUS INTERFACE UNIT For word transfe
Page 93 and 94: BUS INTERFACE UNIT CLKOUT T4 T1 T2
Page 95 and 96: BUS INTERFACE UNIT CLKOUT T4 or TI
Page 97 and 98: BUS INTERFACE UNIT Signals From CPU
Page 99 and 100: BUS INTERFACE UNIT T2 T3 or TW T4 o
Page 101 and 102: BUS INTERFACE UNIT A normally not-r
Page 103 and 104: BUS INTERFACE UNIT T2 or T3 or TW T
Page 105 and 106: BUS INTERFACE UNIT An idle bus stat
Page 107 and 108: BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
Page 109 and 110: BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
Page 111 and 112:
BUS INTERFACE UNIT The minimum devi
Page 113 and 114:
BUS INTERFACE UNIT Figure 3-24 show
Page 115 and 116:
BUS INTERFACE UNIT After several TI
Page 117 and 118:
BUS INTERFACE UNIT 3.5.5 Temporaril
Page 119 and 120:
BUS INTERFACE UNIT CLKOUT ALE T4 T1
Page 121 and 122:
BUS INTERFACE UNIT CLKOUT NMI/NTx N
Page 123 and 124:
BUS INTERFACE UNIT ALE Processor A1
Page 125 and 126:
BUS INTERFACE UNIT The WAIT instruc
Page 127 and 128:
BUS INTERFACE UNIT CLKOUT HOLD 1 2
Page 129 and 130:
BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
Page 131 and 132:
BUS INTERFACE UNIT CLKOUT HOLD 1 2
Page 134:
Peripheral Control Block 4
Page 137 and 138:
PERIPHERAL CONTROL BLOCK Register N
Page 139 and 140:
PERIPHERAL CONTROL BLOCK 4.3 RESERV
Page 141 and 142:
PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
Page 144:
Clock Generation and Power Manageme
Page 147 and 148:
CLOCK GENERATION AND POWER MANAGEME
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 172 and 173:
CHAPTER 6 CHIP-SELECT UNIT Every sy
Page 174 and 175:
CHIP-SELECT UNIT Stop Value Ignore
Page 176 and 177:
CHIP-SELECT UNIT Address 1 Ready Fl
Page 178 and 179:
CHIP-SELECT UNIT Register Name: Reg
Page 180 and 181:
CHIP-SELECT UNIT Register Name: Reg
Page 182 and 183:
CHIP-SELECT UNIT In the previous eq
Page 184 and 185:
CHIP-SELECT UNIT No Any READY = 1 W
Page 186 and 187:
CHIP-SELECT UNIT The GCS chip-selec
Page 188 and 189:
CHIP-SELECT UNIT $ TITLE (Chip-Sele
Page 190 and 191:
CHIP-SELECT UNIT ;SET UP CHIP SELEC
Page 192:
Refresh Control Unit 7
Page 195 and 196:
REFRESH CONTROL UNIT 7.1 THE ROLE O
Page 197 and 198:
REFRESH CONTROL UNIT The BIU does n
Page 199 and 200:
REFRESH CONTROL UNIT CLKOUT T4 T1 T
Page 201 and 202:
REFRESH CONTROL UNIT 7.7.2.1 Refres
Page 203 and 204:
REFRESH CONTROL UNIT Register Name:
Page 205 and 206:
REFRESH CONTROL UNIT $mod186 name e
Page 207 and 208:
REFRESH CONTROL UNIT T1 T1 T1 T1 T1
Page 210 and 211:
CHAPTER 8 INTERRUPT CONTROL UNIT Th
Page 212 and 213:
INTERRUPT CONTROL UNIT Polling requ
Page 214 and 215:
INTERRUPT CONTROL UNIT INT INTA D7:
Page 216 and 217:
INTERRUPT CONTROL UNIT Edge Sense L
Page 218 and 219:
INTERRUPT CONTROL UNIT 8.3.2 Interr
Page 220 and 221:
INTERRUPT CONTROL UNIT 8.3.3.1 Defa
Page 222 and 223:
INTERRUPT CONTROL UNIT More than on
Page 224 and 225:
INTERRUPT CONTROL UNIT IR0 IR1 IR2
Page 226 and 227:
INTERRUPT CONTROL UNIT 10. On the s
Page 228 and 229:
INTERRUPT CONTROL UNIT 8.3.7 Altern
Page 230 and 231:
INTERRUPT CONTROL UNIT 8.4.2 Progra
Page 232 and 233:
INTERRUPT CONTROL UNIT Begin Initia
Page 234 and 235:
INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
Page 236 and 237:
INTERRUPT CONTROL UNIT Register Nam
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
INTERRUPT CONTROL UNIT Table 8-2. O
Page 244 and 245:
INTERRUPT CONTROL UNIT The ESMM (En
Page 246 and 247:
INTERRUPT CONTROL UNIT Internal Int
Page 248 and 249:
INTERRUPT CONTROL UNIT To Slave 825
Page 250 and 251:
Page 252 and 253:
INTERRUPT CONTROL UNIT 8.6.1 Interr
Page 254 and 255:
INTERRUPT CONTROL UNIT CPU WR RD GC
Page 256 and 257:
INTERRUPT CONTROL UNIT Non-Alike Ac
Page 258 and 259:
INTERRUPT CONTROL UNIT ;Now start t
Page 260:
INTERRUPT CONTROL UNIT ;The followi
Page 264 and 265:
CHAPTER 9 TIMER/COUNTER UNIT The Ti
Page 266 and 267:
TIMER/COUNTER UNIT Timer 0 Timer 1
Page 268 and 269:
TIMER/COUNTER UNIT Continued From "
Page 270 and 271:
TIMER/COUNTER UNIT Register Name: R
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
TIMER/COUNTER UNIT The timer counti
Page 278 and 279:
TIMER/COUNTER UNIT Timer 0 Serviced
Page 280 and 281:
TIMER/COUNTER UNIT 9.3.2 Synchroniz
Page 282 and 283:
TIMER/COUNTER UNIT lib_80186 segmen
Page 284 and 285:
TIMER/COUNTER UNIT $mod186 name exa
Page 286:
TIMER/COUNTER UNIT _CMPB equ word p
Page 290 and 291:
CHAPTER 10 DIRECT MEMORY ACCESS UNI
Page 292 and 293:
DIRECT MEMORY ACCESS UNIT 10.1.1.1
Page 294 and 295:
Page 296 and 297:
Page 298 and 299:
DIRECT MEMORY ACCESS UNIT The Chip-
Page 300 and 301:
DIRECT MEMORY ACCESS UNIT Both Requ
Page 302 and 303:
Page 304 and 305:
DIRECT MEMORY ACCESS UNIT Channel a
Page 306 and 307:
DIRECT MEMORY ACCESS UNIT Register
Page 308 and 309:
Page 310 and 311:
Page 312 and 313:
DIRECT MEMORY ACCESS UNIT When inte
Page 314 and 315:
DIRECT MEMORY ACCESS UNIT The trans
Page 316 and 317:
DIRECT MEMORY ACCESS UNIT 10.2.4 Su
Page 318 and 319:
DIRECT MEMORY ACCESS UNIT 10.3.1 DR
Page 320 and 321:
DIRECT MEMORY ACCESS UNIT $MOD186 n
Page 322 and 323:
DIRECT MEMORY ACCESS UNIT SECTORS M
Page 324 and 325:
DIRECT MEMORY ACCESS UNIT XOR AX, A
Page 326 and 327:
DIRECT MEMORY ACCESS UNIT $mod186 n
Page 328:
Serial Communications Unit 11
Page 331 and 332:
SERIAL COMMUNICATIONS UNIT 1 2 3 4
Page 333 and 334:
SERIAL COMMUNICATIONS UNIT The RX m
Page 335 and 336:
SERIAL COMMUNICATIONS UNIT The Tran
Page 337 and 338:
SERIAL COMMUNICATIONS UNIT 5. At th
Page 339 and 340:
SERIAL COMMUNICATIONS UNIT Register
Page 341 and 342:
SERIAL COMMUNICATIONS UNIT Register
Page 343 and 344:
SERIAL COMMUNICATIONS UNIT 3. If th
Page 345 and 346:
SERIAL COMMUNICATIONS UNIT The seri
Page 347 and 348:
SERIAL COMMUNICATIONS UNIT 11.2.3 P
Page 349 and 350:
SERIAL COMMUNICATIONS UNIT BCLK is
Page 351 and 352:
SERIAL COMMUNICATIONS UNIT $mod186
Page 353 and 354:
SERIAL COMMUNICATIONS UNIT mov dx,
Page 355 and 356:
Page 357 and 358:
SERIAL COMMUNICATIONS UNIT mov dx,
Page 359 and 360:
SERIAL COMMUNICATIONS UNIT Disconne
Page 361 and 362:
Page 364 and 365:
CHAPTER 12 WATCHDOG TIMER UNIT Syst
Page 366 and 367:
WATCHDOG TIMER UNIT Figure 12-3(b)
Page 368 and 369:
WATCHDOG TIMER UNIT wdt_data segmen
Page 370 and 371:
WATCHDOG TIMER UNIT A LOCKed instru
Page 372 and 373:
WATCHDOG TIMER UNIT Register Name:
Page 374 and 375:
WATCHDOG TIMER UNIT Register Name:
Page 376:
WATCHDOG TIMER UNIT wdt_data segmen
Page 380 and 381:
CHAPTER 13 INPUT/OUTPUT PORTS Many
Page 382 and 383:
INPUT/OUTPUT PORTS 13.1.2 Output Po
Page 384 and 385:
INPUT/OUTPUT PORTS From Port Direct
Page 386 and 387:
INPUT/OUTPUT PORTS 13.1.4.3 Port 3
Page 388 and 389:
INPUT/OUTPUT PORTS Register Name: R
Page 390 and 391:
INPUT/OUTPUT PORTS Register Name: R
Page 392:
Math Coprocessing 14
Page 395 and 396:
MATH COPROCESSING 14.3 THE 80C187 M
Page 397 and 398:
MATH COPROCESSING Available data ty
Page 399 and 400:
MATH COPROCESSING 14.3.1.5 Constant
Page 401 and 402:
MATH COPROCESSING Increasing Signif
Page 403 and 404:
MATH COPROCESSING 14.4.1 Clocking t
Page 405 and 406:
MATH COPROCESSING External Oscillat
Page 407 and 408:
MATH COPROCESSING 80C186 Modular Co
Page 409 and 410:
MATH COPROCESSING $mod186 $modc187
Page 412:
CHAPTER 15 ONCE MODE ONCE (pronounc
Page 416 and 417:
APPENDIX A 80C186 INSTRUCTION SET A
Page 418 and 419:
80C186 INSTRUCTION SET ADDITIONS AN
Page 420 and 421:
Page 422 and 423:
Page 424 and 425:
Page 426:
Input Synchronization B
Page 429 and 430:
INPUT SYNCHRONIZATION A synchroniza
Page 432 and 433:
APPENDIX C INSTRUCTION SET DESCRIPT
Page 434 and 435:
INSTRUCTION SET DESCRIPTIONS Table
Page 436 and 437:
Page 438 and 439:
Page 440 and 441:
Page 442 and 443:
Page 444 and 445:
Page 446 and 447:
Page 448 and 449:
Page 450 and 451:
Page 452 and 453:
Page 454 and 455:
Page 456 and 457:
Page 458 and 459:
Page 460 and 461:
Page 462 and 463:
INSTRUCTION SET DESCRIPTIONS NEG NO
Page 464 and 465:
Page 466 and 467:
Page 468 and 469:
Page 470 and 471:
Page 472 and 473:
Page 474 and 475:
INSTRUCTION SET DESCRIPTIONS SHR ST
Page 476 and 477:
Page 478:
Page 482 and 483:
APPENDIX D INSTRUCTION SET OPCODES
Page 484 and 485:
INSTRUCTION SET OPCODES AND CLOCK C
Page 486 and 487:
Page 488 and 489:
Page 490 and 491:
Page 492 and 493:
Page 494 and 495:
Page 496 and 497:
Page 498 and 499:
Page 500 and 501:
Page 502 and 503:
Page 504:
Index
Page 507 and 508:
INDEX AH register, 2-5 AL register,
Page 509 and 510:
INDEX synchronization, 10-23 transf
Page 511 and 512:
INDEX NMI, 2-42 generating with WDT
Page 513 and 514:
INDEX bus latency, 7-7 calculating
Page 515:
INDEX Trap exceptions, 2-42 Trap Fl
show all

80C186EC/80C188EC Microprocessor User's Manual

Create successful ePaper yourself

Delete template?

Save as template?