80C186EC/80C188EC Microprocessor User's Manual

SERIAL COMMUNICATIONS UNIT
BCLK is an asynchronous input. However, the pin does have setup and hold times, which guarantee
recognition at a specific CLKOUT. If the BCLK input signal has high and low times that
are both at least 1½ CLKOUT periods, than synchronization to CLKOUT is not necessary. However,
when the BCLK signal has a high or a low time of less than 1½ CLKOUT periods, meeting
the setup and hold times to CLKOUT is necessary to avoid missing BCLK transitions. The maximum
input frequency to BCLK is one-half the frequency of CLKOUT (CPU operating frequency).
11.3.3 Mode 0 Timings
This section shows the timings of the TXD and RXD pins in Mode 0. In Mode 0, TXD never
floats. When not transmitting or receiving, TXD is high. RXD floats except when transmitting a
character.
11.3.3.1 CLKOUT as Baud Timebase Clock
The behavior of the transmit/receive clock (on TXD) is governed by the value of BxCMP. When
the BxCMP value is greater than or equal to two. The TXD pin is low for two CLKOUT periods
and is high for (BxCMP – 1) CLKOUT periods (see Figure 11-17). BxCMP cannot be equal to a
one, otherwise the serial port buffer registers (SxRBUF) will not receive the correct data.
CLKOUT
TXD
Low For
2 Clocks
High For
N-1 Clocks
RXD
BIT 0
BIT 1
A1282-A
Figure 11-17. Mode 0, BxCMP > 2
For transmissions, the RXD pin changes on the next CLKOUT falling edge following a low-tohigh
transition on TXD. Therefore, the data on the RXD pin is guaranteed to be valid on the rising
edges of TXD. Use the rising edge of TXD to latch the value on RXD. For receptions, the incoming
serial data must meet the setup and hold timings with respect to the rising edge of TXD. These
timings can be found in the AC timings section of the data sheet.
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