80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
Register Name:
Register Mnemonic:
Register Function:
Timer Interrupt Request Latch
TIMIRL
Latches Timer/Counter Unit interrupt requests.
15 0
M
S
K
3
M
S
K
2
M
S
K
1
M
S
K
0
T
I
R
2
T
I
R
1
T
I
R
0
A1235-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
TIR2:0
Timer
Interrupt
Request
0H
The corresponding timer sets a bit in this
register to post an interrupt request. These bits
must be cleared to deassert the IR signal to the
8259A module.
MSK2:0
IR Latch
Clear Mask
XH
This bit must be set to modify the state of the
associated TIR2:0 bit. The MSK2:0 bits are
safeguards against accidentally clearing a
pending interrupt request. These bits are write
only.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-26. Timer Interrupt Request Latch Register
8.6 HARDWARE CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT
This section covers hardware interface information for the Interrupt Control Unit. Specific timing
values are not presented, as these are subject to change. Consult the most recent version of the
data sheet for timing information.
8-42