80C186EC/80C188EC Microprocessor User's Manual

CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
Chip-Select Stop Register
UCSSP, LCSSP, GCSxSP (x=0-7)
Defines chip-select stop address and other control
functions.
15 0
C
S
9
C
S
8
C
S
7
C
S
6
C
S
5
C
S
4
C
S
3
C
S
2
C
S
1
C
S
0
C
S
E
N
I
S
T
O
P
M
E
M
R
D
Y
A1164-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
MEM
RDY
Bus Cycle
Selector
Bus Ready
Enable
1 When MEM is set, the chip-select goes active
for memory bus cycles. Clearing MEM activates
the chip-select for I/O bus cycles.
MEM defines which address bits are used by
the start and stop address comparators. When
MEM is cleared, address bits A15:6 are routed
to the comparators. When MEM is set, address
bits A19:10 are routed to the comparators.
1 Setting RDY requires that bus ready be active
to complete a bus cycle. Bus ready is ignored
when RDY is cleared. RDY must be set to
extend wait states beyond the number
determined by WS3:0.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. The reset state of
CSEN and ISTOP is ‘1’ for the UCSSP register.
Figure 6-6. STOP Register Definition (Continued)
The correct sequence to program a non-enabled chip-select is as follows. (If the chip-select is already
enabled, either reverse the sequence or disable the chip-select before reprogramming it.)
1. Program the START register
2. Program the STOP register
6-9