80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
The transfer count (the number of transfers desired) is written to the DMA Transfer Count Register.
The Transfer Count Register is 16 bits wide, limiting the total number of transfers for a
channel to 65,536 (without reprogramming). The Transfer Count Register is decremented by one
after each transfer (for both byte and word transfers).
Register Name:
Register Mnemonic:
Register Function:
DMA Transfer Count
DxTC
Contains the DMA channel’s transfer count.
15 0
T
C
1
5
T
C
1
4
T
C
1
3
T
C
1
2
T
C
1
1
T
C
1
0
T
C
9
T
C
8
T
C
7
T
C
6
T
C
5
T
C
4
T
C
3
T
C
2
T
C
1
T
C
0
A1172-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
TC15:0
Transfer
Count
XXXXH
Contains the transfer count for a DMA channel.
This value is decremented by one after each
transfer.
Figure 10-15. Transfer Count Register
The TC bit, when set, instructs the DMA channel to disarm itself (by clearing the STRT bit) when
the transfer count reaches zero. If the TC bit is cleared, the channel continues to perform transfers
regardless of the state of the Transfer Count Register. Unsynchronized (software-initiated) transfers
always terminate when the transfer count reaches zero; the TC bit is ignored.
10.2.1.7 Generating Interrupts on Terminal Count
A channel can be programmed to generate an interrupt request whenever the transfer count reaches
zero. Both the TC bit and the INT bit in the DMA Control Register (Figure 10-13 on page
10-20) must be set to generate an interrupt request.
10-25