80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
BIU Request
T
2
D
R
Q
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0
D
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Q
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0
D
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Q
Module A
Request
Inter-Module
Arbitration
Logic
Module B
Request
R
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1
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1
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Inter-Channel Arbitration
and
Internal Request Multiplexer
Inter-Channel Arbitration
and
Internal Request Multiplexer
Channel 0
Channel 1 Channel 0 Channel 1
Module A
Module B
DRQ0
DRQ1
DRQ2
DRQ3
A1184-0A
Figure 10-8. 80C186EC/C188EC DMA Unit
Like inter-channel priority, DMA module priority is set on a relative basis: one module may be
set higher than or equal to the other module.
Priority arbitration between modules is subject to the same rules as arbitration between channels.
When priority is fixed between modules (i.e., one module is set to a higher priority than the other),
the high-priority module continues to perform transfers as long as its DMA request is active, the
transfers have not been suspended or terminated and it has not released the bus.
The DMA modules rotate priority when both modules are set to the same priority. DMA module
B is initially set to high priority and module A is set to low priority. After a channel within a module
performs a transfer, the module is set to low priority.
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