80C186EC/80C188EC Microprocessor User's Manual

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INDEX P Packed BCD, defined, 2-37 Packed decimal, defined, 14-7 Parity Flag (PF), 2-7, 2-9 PCB Relocation Register, 4-1, 4-3, 4-6 and math coprocessing, 14-1 PDTMR pin, 5-18 Peripheral Control Block (PCB), 4-1 8259A register access ports, 8-21 accessing, 4-4 and DMA Unit, 10-3 and F-Bus operation, 4-5 base address, 4-6–4-7 bus cycles, 4-4 READY signals, 4-4 reserved locations, 4-6 wait states, 4-4 Peripheral control registers, 4-1, 4-6 Pointer, defined, 2-37 Poll Status Byte, 8-35 Polling and 8259A initialization, 8-35 overview, 8-3 with the Poll command, 8-20, 8-34 POPA instruction, A-1 Port Control Register (PxCON), 13-8 Port Data Latch Register (PxLTCH), 13-10 Port Direction Register (PxDIR), 13-9 Port Pin State Register (PxPIN), 13-11 Power consumption‚ reducing, 3-29, 5-24 Power Control Register, 5-12 Power management, 5-10–5-24 Power management modes and HALT bus cycles, 3-29, 3-32, 3-34 compared, 5-24 Powerdown mode, 5-16–5-19, 7-2 and bus cycles, 5-16 control register, 5-12 entering, 5-17 exiting, 5-18–5-19 exiting HALT bus cycle, 3-35 initialization code, 5-15–5-19 Power-Save mode, 5-19–5-23, 7-2 and DRAM refresh rate, 5-22 and refresh interval, 7-7 control register, 5-21 entering, 5-20 exiting, 5-22 initialization code, 5-22–5-23 Power-Save Register, 5-21 Priority cell‚ See Interrupts Priority Resolver, 8-10 Processor control instructions, 2-27 Processor Status Word (PSW), 2-1, 2-7, 2-41 bits defined, 2-7, 2-9 flag storage formats, 2-19 reset status, 2-7 Program transfer instructions, 2-23–2-24 conditional transfers, 2-24, 2-26 interrupts, 2-26 iteration control, 2-25 unconditional transfers, 2-24 Programming examples‚ See Software PUSH instruction, A-8 PUSHA instruction, A-1 R RCL instruction, A-10 RCR instruction, A-10 Read bus cycles‚ See Bus cycles READY and chip-selects, 6-11 and internal 8259A modules, 8-44 and normally not-ready signal, 3-16–3-18 and normally ready signal, 3-16–3-17 and PCB accesses, 4-4 and wait states, 3-13–3-18 block diagram, 3-15 implementation approaches, 3-13 timing concerns, 3-17 Real, defined, 14-7 Real-time clock, code example, 9-17–9-20 Refresh address, 7-4 Refresh Address Register (RFADDR), 7-10 Refresh Base Address Register (RFBASE), 7-8 Refresh bus cycle‚ See Bus cycles Refresh Clock Interval Register (RFTIME), 7-7, 7-8 Refresh Control Register (RFCON), 7-9, 7-10 Refresh Control Unit (RCU), 7-1–7-14 and bus hold protocol, 7-13–7-14 and Powerdown mode, 7-2 and Power-Save mode, 5-20, 7-2, 7-7 block diagram, 7-1 Index-7
INDEX bus latency, 7-7 calculating refresh interval, 7-7 control registers, 7-7–7-10 initialization code, 7-11 operation, 7-2 overview, 7-2–7-4 programming, 7-7–7-12 relationship to BIU, 7-1 Register operands, 2-27 Registers, 2-1 control, 2-1 data, 2-4, 2-5 general, 2-1, 2-4, 2-5 H & L group, 2-4 index, 2-5, 2-13, 2-34 P & I group, 2-4 pointer, 2-1, 2-5, 2-13 pointer and index, 2-4 segment, 2-1, 2-5, 2-11, 2-12 status, 2-1 Relocation Register‚ See PCB Relocation Register Reset and bus hold protocol, 5-6 and clock synchronization, 5-6–5-10 cold, 5-7, 5-8 RC circuit for reset input, 5-7 warm, 5-7, 5-9 with Watchdog Timer, 12-1 ROL instruction, A-10 ROR instruction, A-10 S SAL instruction, A-9 SAR instruction, A-9 Serial Communications Unit (SCU) and DMA, 10-26 asynchronous communications, 11-1–11-8, 11-13–11-17 example, 11-21–11-24 mode 1, 11-6 mode 2, 11-7 mode 3, 11-6 mode 4, 11-6 baud rates, 11-10–11-13 baud timebase clock, 11-20, 11-21 BCLK pin timings, 11-18–11-20 break characters, 11-4, 11-14 CTS# pin timings, 11-18 examples, 11-21–11-32 features, 11-1 framing errors, 11-4 hardware considerations, 11-18–11-21 Interrupt Request Latch Register (SCUIRL), 8-41 interrupts, 11-21 master/slave example, 11-24–11-32 multiplexed I/O port pins, 13-6–13-7 multiprocessor communications, 11-14 overrun errors, 11-4 overview, 11-1–11-8 parity errors, 11-4 programming, 11-9–11-18 receiver, 11-2 RX machine, 11-2 stand-alone communications, 11-13 synchronous communications, 11-8, 11-18 example, 11-23 timings, 11-20 transmitter, 11-4 TX machine, 11-4 Serial Port Control Register (SxCON), 11-15 Serial Port Status Register (SxSTS), 11-16, 11-17 Serial ports‚ See Serial Communications Unit (SCU) Serial Receive Buffer Register (SxRBUF), 11-9 Serial Transmit Buffer Register (SxTBUF), 11-10 SHL instruction, A-9 Short integer, defined, 14-7 Short real, defined, 14-7 SHR instruction, A-9 SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Sign Flag (SF), 2-7, 2-9 Single-step trap (Type 1 exception), 2-43 Slave ID, 8-17 register (ICW3), 8-26, 8-28 Software code example 80C187 floating-point routine, 14-16 80C187 initialization, 14-13–14-15 digital one-shot, 9-17–9-23 DMA initialization, 10-30–10-38 DMA-driven serial transfers, 10-30 I/O port configuration, 13-12 real-time clock, 9-17–9-19 Index-8
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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Page 462 and 463: INSTRUCTION SET DESCRIPTIONS NEG NO
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Page 474 and 475: INSTRUCTION SET DESCRIPTIONS SHR ST
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Page 482 and 483: APPENDIX D INSTRUCTION SET OPCODES
Page 484 and 485: INSTRUCTION SET OPCODES AND CLOCK C
Page 504: Index
Page 507 and 508: INDEX AH register, 2-5 AL register,
Page 509 and 510: INDEX synchronization, 10-23 transf
Page 511: INDEX NMI, 2-42 generating with WDT
Page 515: INDEX Trap exceptions, 2-42 Trap Fl
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