80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
CLKOUT
HOLD
1
2
4
HLDA
3
AD15:0
DEN
A19:16
RD,WR
DT/R
S2:0,BHE
LOCK
Float
Float
NOTES:
1. T
CLIS
: HOLD input to clock low
2. T
CHOF
: Clock high to output float
3. T
CLOF
: Clock low to output float
4. T
CLOV
: Clock low to HLDA high
A1097-0A
Figure 3-34. Timing Sequence Entering HOLD
Table 3-7. Signal Condition Entering HOLD
Signal
A19:16, S2:0, RD, WR, DT/R, BHE (RFSH), LOCK
AD15:0 (16-bit), AD7:0 (8-bit), A15:8 (8-bit), DEN
HOLD Condition
These signals float one-half clock before HLDA
is generated (i.e., phase 2).
These signals float during the same clock in
which HLDA is generated (i.e., phase 1).
3.7.1.1 HOLD Bus Latency
The duration between the time that the external device asserts HOLD and the time that the BIU
asserts HLDA is known as bus latency. In Figure 3-34, the two-clock delay between HOLD and
HLDA represents the shortest bus latency. Normally this occurs only if the bus is idle or halted
or if the bus hold request occurs just before the BIU begins another bus cycle.
3-42