80C186EC/80C188EC Microprocessor User's Manual

INPUT/OUTPUT PORTS
Register Name:
Register Mnemonic:
Register Function:
Port Direction Register
PxDIR (P1DIR, P2DIR, P3DIR)
Controls the direction of pins programmed as I/O
ports.
15 0
P
D
7
P
D
6
P
D
5
P
D
4
P
D
3
P
D
2
P
D
1
P
D
0
A1313-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
PD7:0
Port
Direction 7:0
FFH
Setting the PD bit for a pin programmed as a
general-purpose I/O port selects the pin as an
input. Clearing the PD bit selects the pin as an
output.
NOTES:
1) PD7 and PD6 do not exist for Port 3.
2) The PD bits for Port 1 and P3.0 through P3.3
are ignored and can be used as storage.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 13-5. Port Direction Register (PxDIR)
13.2.3 Port Data Latch Register
The Port Data Latch Register (Figure 13-6) holds the value to be driven on an output or bidirectional
pin. This value appears at the pin only if it is programmed as a port.
The Port Data Latch Register is read/write. Reading a Port Data Latch Register returns the value
of the latch itself and not that of the associated port pin.
13-9