80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.5.1.4 Using the Interrupt Request Latch Registers to Debug Interrupt Handlers
Software can set as well as clear the individual Interrupt Request Latch bits. Setting an Interrupt
Request Latch bit posts an interrupt request just as if the on-chip peripheral had requested an
interrupt. This feature allows the debugging of interrupt handlers independent of peripheral
function. A serial port interrupt handler, for example, could be debugged by initiating simulated
interrupts rather than connecting the necessary hardware to the serial port. Setting the Interrupt
Request Latch bit for DMA channel 0, DMA channel 1 or Serial channel 1 activates the corresponding
interrupt output, but the interrupt outputs must still be tied back to a processor interrupt
input.
Register Name:
Register Mnemonic:
Register Function:
DMA Interrupt Request Latch
DMAIRL
Latches DMA interrupt requests.
15 0
M
S
K
3
M
S
K
2
M
S
K
1
M
S
K
0
D
M
I
R
3
D
M
I
R
2
D
M
I
R
1
D
M
I
R
0
A1233-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
DMIR3:0
DMA
Interrupt
Request
0H
The corresponding DMA channel sets a bit in
this register to post an interrupt request. These
bits must be cleared to deassert the IR signal to
the 8259A module or to the Port 3 Multiplexer.
MSK3:0
IR Latch
Clear Mask
XH
This bit must be set to modify the state of the
associated DMIR3:0 bit. The MSK3:0 bits are
safeguards against accidentally clearing a
pending interrupt request. These bits are write
only.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-24. DMA Interrupt Request Latch Register
8-40