80C186EC/80C188EC Microprocessor User's Manual

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit
sequentially prefetches instructions from memory. As long as the prefetch queue is partially full,
the Execution Unit fetches instructions.
2.1.3 General Registers
The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The
general registers are subdivided into two sets of four registers. These sets are the data registers
(also called the H & L group for high and low) and the pointer and index registers (also called the
P & I group).
15
H
8 7
L
0
AH
AX
AL
Accumulator
Data
Group
BH
CH
BX
CX
BL
CL
Base
Count
DH
DX
DL
Data
SP
Stack Pointer
Pointer
and
Index
Group
BP
SI
Base Pointer
Source Index
DI
Destination Index
A1033-0A
Figure 2-3. General Registers
2-4