80C186EC/80C188EC Microprocessor User's Manual

CLOCK GENERATION AND POWER MANAGEMENT
CLKOUT
T2 T3 T4
WR
1
2
NOTES:
1. : Write to Power-Save Register (as viewed on the bus).
2. : Low-going edge of T3 starts new clock rate.
A1124-0A
Figure 5-15. Power-Save Clock Transition
5.2.3.2 Leaving Power-Save Mode
Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in
the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.
When the PSEN bit clears, the clock returns to its undivided frequency (standard divide-by-two)
at the falling T3 edge of the write to the Power-Save Register. The same result happens from reprogramming
the clock divisor to a new value. The Power-Save Register can be read or written
at any time.
Unmasked interrupts include those from the Interrupt Control Unit, but not software interrupts.
If an NMI occurs, or an unmasked interrupt request has sufficient priority to pass to the core,
Power-Save mode will end. The PSEN bit clears and the clock resumes full-speed operation at
the falling edge of a bus cycle T3 state. However, the exact bus cycle of the transition is undefined.
The Return from Interrupt instruction (IRET) does not automatically set the PSEN bit
again. If you still want Power-Save mode operation, you can set the PSEN bit as part of the interrupt
service routine.
5.2.3.3 Example Power-Save Initialization Code
Example 5-2 illustrates programming the Power-Save Unit for a typical system. The program also
includes code to change the DRAM refresh rate to compensate for the reduced clock rate.
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