80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.3.6.2 The Cascaded Interrupt Acknowledge Cycle: An Example
The following example illustrates the interaction between master and slave 8259A modules in a
cascaded configuration. We assume the following conditions:
• The master 8259A module is programmed for cascade operation, a slave on IR7, default
priority and edge-triggered mode.
• The slave 8259A module is programmed for cascade operation, a slave address of 7, default
priority and edge-triggered mode.
• Both modules have just been initialized and no interrupts are pending.
• All interrupts in both modules are unmasked.
A typical cascade interrupt sequence takes place as follows:
1. A low-to-high transition on IR2 of the slave 8259A module sets bit 2 in the Interrupt
Request Register.
2. The slave’s Priority Resolver checks whether any bits are set in the Interrupt Request
Register that are of a higher priority than IR2. There are none.
3. The slave’s Priority Resolver checks whether any bits are set in the In-Service Register
that are of an equal or higher priority than IR2. There are none.
4. At this point, the slave’s Priority Resolver has determined that IR2 has sufficient priority
to request an interrupt. The slave interrupt request line (connected to the IR7 line on the
master 8259A module) is asserted to signal an interrupt request.
5. The low-to-high transition on the IR7 line signals to the master that the slave module is
requesting an interrupt.
6. The Priority Resolver within the master 8259A module checks whether the slave request
is of sufficient priority to interrupt the CPU. (It is.) Note that, for the purposes of priority
resolution, a cascaded input looks just like any other IR line.
7. The master 8259A module asserts the interrupt request output line to the CPU.
8. The CPU signals acknowledgment of the interrupt by initiating an interrupt acknowledge
(INTA) cycle.
9. On the first falling edge of INTA, the following actions occur:
— The master 8259A module clears the IR7 Interrupt Request Bit and sets the IR7 In-
Service Bit.
— The master 8259A module sees that IR7 has a slave connected to it and drives the
address of the slave (seven, in this case) on the CAS2:0 lines.
— The slave 8259A module recognizes its address on the CAS2:0 bus. The slave 8259A
module clears the IR2 Interrupt Request Bit and sets the IR2 In-Service bit.
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