80C186EC/80C188EC Microprocessor User's Manual

CLOCK GENERATION AND POWER MANAGEMENT
5.2.2.2 Leaving Powerdown Mode
An NMI, unmasked interrupt, or reset returns the processor to Active mode. Unlike other 80C186
Modular Core family members, the processor does not have clocked logic in the Interrupt Control
Unit.
If the device leaves Powerdown mode by an NMI or unmasked interrupt, a delay must follow the
interrupt request to allow the crystal oscillator to stabilize before gating it to the internal phase
clocks. An external timing pin sets this delay as described below. Leaving Powerdown by an unmasked
interrupt or NMI does not clear the PWRDN bit in the Power Control Register. A reset
also takes the processor out of Powerdown mode. Since the oscillator is off, the user should follow
the oscillator cold start guidelines (see “Reset and Clock Synchronization” on page 5-6).
The Powerdown timer circuit (Figure 5-13) has a PDTMR pin. Connecting this pin to an external
capacitor gives the user control over the gating of the crystal oscillator to the internal clocks. The
strong P-channel device is always on except during exit from Powerdown mode. This pullup
keeps the powerdown capacitor C PD charged up to V CC . When the processor detects an interrupt
or NMI, the weak N-channel device turns on and the P-channel turns off. Leaving Powerdown by
an unmasked interrupt or NMI does not clear the PWRDN bit in the Power Control Register. C PD
discharges slowly. At the same time, the circuit turns on the feedback inverter on the crystal oscillator
and oscillation starts.
The Schmitt trigger connected to the PDTMR pin asserts the internal OSC_OK signal when the
voltage at the pin drops below its switching threshold. The OSC_OK signal gates the crystal oscillator
output to the internal clock circuitry. One CLKOUT cycle runs before the internal clocks
turn back on. It takes two additional CLKOUT cycles for an NMI request to reach the CPU and
another six clocks for the vector to be fetched. An unmasked interrupt request reaches the CPU
two clocks after the Interrupt Control Unit resolution time, and the first INTA cycle starts six
clocks later.
5-18