80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.4.4.3 Special Mask Mode, Poll Mode and Register Reading: OCW3
OCW3 (Figure 8-19) is used to control Special Mask Mode, Poll Mode, and register reading.
Register Name: Operation Command Word 3
Register Mnemonic: OCW3 (accessed through MPICP0, SPICP0)
Register Function: Controls Special Mask Mode and register reading.
15 0
0
E
S
M
M
S
M
M
0
1
P
O
L
L
E
R
R
R
S
E
L
A1227-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
ESMM
Enable
Special
Mask Mode
X
ESMM must be set to modify SMM.
SMM
Special
Mask Mode
X
Set SMM to select Special Mask Mode (allows
lower-priority interrupts to interrupt higherpriority
handlers).
POLL
Poll
Command
X
Setting this bit starts the polling sequence.
Polling always takes precedence over reading
the 8259A registers.
ERR
Enable
Register
Read
X
ERR must be set to modify RSEL.
RSEL
Read
Register
Select
X
RSEL chooses which register is read during the
next read cycle. When RSEL is set, the In-
Service Register is read; when RSEL is
cleared, the Interrupt Request Register is read.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-19. OCW3 Register
8-34