80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.6.1 Interrupt Latency and Response Time
Interrupt latency is the time required for the CPU to begin the interrupt acknowledge sequence
once an unmasked external interrupt is presented. Interrupt response time is the amount of time
necessary to complete the interrupt acknowledge cycle and transfer program control to the interrupt
handler.
The 8259A modules add a finite delay to the interrupt latency. The 8259A modules are asynchronous;
the path through the module is modeled as a purely combinatorial delay known as the Interrupt
Resolution Time (T IRES ). The Interrupt Resolution Time is defined as the delay from an IR
line being asserted to the interrupt request output going active (Figure 8-27). An interrupt request
on the slave 8259A module must travel through two 8259A units (the slave and the master) and
therefore has twice the interrupt resolution delay (2 × T IRES )
IR Line
INT Output of
8259A Module
T IRES
A1236-0A
Figure 8-27. Interrupt Resolution Time
8.6.2 Resetting the Edge Detector
When programmed for edge triggered mode, the 8259A module activates an edge-detection circuit
that sits between the IR lines and the Interrupt Request Register (see Figure 8-4 on page 8-7).
The edge-detection circuit is reset in one of two ways: during initialization of the module or by
deasserting the IR line.
The edge-detection circuit requires that the IR line be held low for a minimum amount of time
(T IRLH ) in order to reset properly (see Figure 8-28). Failure to meet the specification for minimum
low time prevents generation of further interrupts from an interrupt source.
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