80C186EC/80C188EC Microprocessor User's Manual

CLOCK GENERATION AND POWER MANAGEMENT
There are three power management modes: Idle, Powerdown and Power-Save. Power-Save mode
is a clock generation function, while Idle and Powerdown modes are clock distribution functions.
For this discussion, Active mode is the condition of no programmed power management. Active
mode operation feeds the clock signal to the CPU core and all the integrated peripherals and power
consumption reaches its maximum for the application. The processor defaults to Active mode
at reset.
5.2.1 Idle Mode
During Idle mode operation, the clock signal is routed only to the integrated peripheral devices.
CLKOUT continues toggling. The clocks to the CPU core (Execution and Bus Interface Units)
freeze in a logic low state. Idle mode reduces current consumption by about a third, depending
on the activity in the peripheral units.
5.2.1.1 Entering Idle Mode
Setting the appropriate bit in the Power Control Register (Figure 5-9) prepares for Idle mode. The
processor enters Idle mode when it executes the HLT (halt) instruction. If the program arms both
Idle mode and Powerdown mode by mistake, the device halts but remains in Active mode. See
Chapter 3, “Bus Interface Unit,” for detailed information on HALT bus cycles. Figure 5-10
shows some internal and external waveforms during entry into Idle mode.
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