80C186EC/80C188EC Microprocessor User's Manual

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INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4. Mnemonic Encoding Matrix (Right Half) x8 x9 xA xB xC xD xE xF OR b,f,r/m SBB b,f,r/m SUB b,f,r/m CMP b,f,r/m DEC AX POP AX PUSH OR w,f,r/m SBB w,f,r/m SUB w,f,r/m CMP w,f,r/m DEC CX POP CX IMUL OR b,t,r/m SBB b,t,r/m SUB b,t,r/m CMP b,t,r/m DEC DX POP DX PUSH w,i w,i b,i JS JNS JP/ JPE OR w,t,r/m SBB w,t,r/m SUB w,t,r/m CMP w,t,r/m DEC BX POP BX IMUL w,i JNP/ JPO OR b,i SBB b,i SUB b,i CMP b,i DEC SP POP SP INS b JL/ JNGE OR w,i SBB w,i SUB w,i CMP w,i DEC BP POP BP INS w JNL/ JGE PUSH CS PUSH DS SEG =CS SEG =DS DEC SI POP SI OUTS b JLE/ JNG POP DS DAS AAS DEC DI POP DI OUTS w JNLE/ JG 0x 1x 2x 3x 4x 5x 6x 7x MOV b,f,r/m MOV w,f,r/m MOV b,t,r/m MOV w,t,r/m MOV sr,f,r/m LEA MOV sr,t,r/m POP r/m CBW CWD CALL WAIT PUSHF POPF SAHF LAHF L,D TEST TEST STOS STOS LODS LODS SCAS SCAS b,ia w,ia MOV MOV MOV MOV MOV MOV MOV MOV i→AX i→CX i→DX i→BX i→SP i→BP i→SI i→DI ENTER LEAVE RET RET INT INT INTO IRET l(i+SP) l type 3 (any) ESC ESC ESC ESC ESC ESC ESC ESC 0 1 2 3 4 5 6 7 CALL JMP JMP JMP IN IN OUT OUT 8x 9x Ax Bx Cx Dx Ex CLC STC CLI STI CLS STD Grp2 b,r/m Grp2 w,r/m Fx NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes. D-21
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Definition Abbr Definition Abbr Definition Abbr Definition b byte operation ia immediate to accumulator m memory t to CPU register d direct id indirect r/m EA is second byte v variable f from CPU register is immediate byte, sign extended si short intrasegment w word operation i immediate l long (intersegment) sr segment register z zero Byte 2 Immed Shift Grp1 Grp2 mod 000 r/m ADD ROL TEST INC mod 001 r/m OR ROR — DEC mod 010 r/m ADC RCL NOT CALL id mod 011 r/m SBB RCR NEG CALL l, id mod 100 r/m AND SHL/SAL MUL JMP id mod 101 r/m SUB SHR IMUL JMP i, id mod 110 r/m XOR — DIV PUSH mod 111 r/m CMP SAR IDIV — mod and r/m determine the Effective Address (EA) calculation. See Table D-1 for definitions. D-22
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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Page 452 and 453: INSTRUCTION SET DESCRIPTIONS Table
Page 462 and 463: INSTRUCTION SET DESCRIPTIONS NEG NO
Page 474 and 475: INSTRUCTION SET DESCRIPTIONS SHR ST
Page 478: INSTRUCTION SET DESCRIPTIONS Table
Page 482 and 483: APPENDIX D INSTRUCTION SET OPCODES
Page 484 and 485: INSTRUCTION SET OPCODES AND CLOCK C
Page 504: Index
Page 507 and 508: INDEX AH register, 2-5 AL register,
Page 509 and 510: INDEX synchronization, 10-23 transf
Page 511 and 512: INDEX NMI, 2-42 generating with WDT
Page 513 and 514: INDEX bus latency, 7-7 calculating
Page 515: INDEX Trap exceptions, 2-42 Trap Fl
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