80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
When internal DMA requests are selected, the source of the internal request must be programmed.
The Internal DMA Request Multiplexer is programmable on a module basis only. The
two channels in a module can be programmed to both respond to Timer 2 or both respond to the
serial port. A module cannot be programmed to have one channel respond to Timer 2 and one
channel respond to the serial port. The source of internal DMA requests for each module is controlled
by the IDRQA and IDRQB bits in the DMA Priority Register (see Figure 10-14).
10.2.1.4 Arming the DMA Channel
Each DMA channel must be armed before it can recognize DMA requests. A channel is armed
by setting its STRT (Start) bit in the DMA Control Register (Figure 10-13 on page 10-20). The
STRT bit can be modified only if the CHG (Change Start) bit is set at the same time. The CHG
bit is a safeguard to prevent accidentally arming a DMA channel while modifying other channel
parameters.
A DMA channel is disarmed by clearing its STRT bit. The STRT bit is cleared either directly by
software or by the channel itself when it is programmed to terminate on terminal count.
10.2.1.5 Selecting Channel Synchronization
The synchronization method for a channel is controlled by the SYN1:0 bits in the DMA Control
Register (Figure 10-13 on page 10-20).
NOTE
The combination SYN1:0=11 is reserved and will result in unpredictable
operation. When IDRQ is set (internal requests selected) the channel must
always be programmed for source-synchronized transfers (SYN1:0=01).
When programmed for unsynchronized transfers (SYN1:0=00), the DMA channel will begin to
transfer data as soon as the STRT bit is set.
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