80C186EC/80C188EC Microprocessor User's Manual

CONTENTS
FIGURES
Figure
Page
8-29 Typical Cascade Connection for 82C59A-2 ...............................................................8-45
8-30 Software Wait State for External 82C59A-2 ...............................................................8-46
9-1 Timer/Counter Unit Block Diagram...............................................................................9-2
9-2 Counter Element Multiplexing and Timer Input Synchronization..................................9-3
9-3 Timers 0 and 1 Flow Chart ...........................................................................................9-4
9-4 Timer/Counter Unit Output Modes................................................................................9-6
9-5 Timer 0 and Timer 1 Control Registers ........................................................................9-7
9-6 Timer 2 Control Register ..............................................................................................9-9
9-7 Timer Count Registers................................................................................................9-10
9-8 Timer Maxcount Compare Registers..........................................................................9-11
9-9 TxOUT Signal Timing .................................................................................................9-15
10-1 Typical DMA Transfer.................................................................................................10-2
10-2 DMA Request Minimum Response Time ...................................................................10-4
10-3 Source-Synchronized Transfers.................................................................................10-5
10-4 Destination-Synchronized Transfers ..........................................................................10-6
10-5 Two-Channel DMA Module ......................................................................................10-10
10-6 Examples of DMA Priority.........................................................................................10-11
10-7 Internal DMA Request Multiplexer............................................................................10-12
10-8 80C186EC/C188EC DMA Unit.................................................................................10-14
10-9 DMA Source Pointer (High-Order Bits).....................................................................10-16
10-10 DMA Source Pointer (Low-Order Bits) .....................................................................10-17
10-11 DMA Destination Pointer (High-Order Bits)..............................................................10-18
10-12 DMA Destination Pointer (Low-Order Bits)...............................................................10-19
10-13 DMA Control Register...............................................................................................10-20
10-14 DMA Module Priority Register ..................................................................................10-24
10-15 Transfer Count Register ...........................................................................................10-25
10-16 DMA Module HALT Register ....................................................................................10-28
11-1 Typical 10-Bit Asynchronous Data Frame..................................................................11-2
11-2 RX Machine................................................................................................................11-3
11-3 TX Machine ................................................................................................................11-5
11-4 Mode 1 Waveform ......................................................................................................11-6
11-5 Mode 3 Waveform ......................................................................................................11-7
11-6 Mode 4 Waveform ......................................................................................................11-7
11-7 Mode 0 Waveforms ....................................................................................................11-8
11-8 Serial Receive Buffer Register (SxRBUF)..................................................................11-9
11-9 Serial Transmit Buffer Register (SxTBUF) ...............................................................11-10
11-10 Baud Rate Counter Register (BxCNT) .....................................................................11-11
11-11 Baud Rate Compare Register (BxCMP)...................................................................11-12
11-12 Calculating the BxCMP Value for a Specific Baud Rate...........................................11-12
11-13 Serial Port Control Register (SxCON) ......................................................................11-15
11-14 Serial Port Status Register (SxSTS).........................................................................11-16
11-15 CTS Recognition Sequence .....................................................................................11-19
11-16 BCLK Synchronization .............................................................................................11-19
11-17 Mode 0, BxCMP > 2 .................................................................................................11-20
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