80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
UCS
AD7:0
LA15:1
CE
O0-7
A 0-14
27C256
RD
OE
OE
AD15:8
A 0-14
O0-7
27C256
CE
Note: A and BHE are not used.
0
A1105-0A
Figure 3-20. Read-Only Device Interface
3.5.2 Write Bus Cycles
Figure 3-21 illustrates a typical write bus cycle. The bus cycle starts with the transition of ALE
high and the generation of valid status bits S2:0. The bus cycle ends when WR transitions high
(inactive), although data remains valid for one additional clock. Table 3-4 lists the two types of
write bus cycles.
3-23