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80C186EC/80C188EC Microprocessor User's Manual

80C186EC/80C188EC Microprocessor User's Manual

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DIRECT MEMORY ACCESS UNIT<br />

10.1.5.3 Serial Communications Unit Transfers<br />

The Serial Communications Unit has two channels, each with its own receiver and transmitter.<br />

Each of the DMA channels is assigned a Serial Communications Unit channel as follows:<br />

• DMA channel 0 supports the serial port 0 transmitter (TX0).<br />

• DMA channel 1 supports the serial port 0 receiver (RX0).<br />

• DMA channel 2 supports the serial port 1 transmitter (TX1).<br />

• DMA channel 3 supports the serial port 1 receiver (RX1).<br />

The DMA request and interrupt request signals from the serial channels are identical. For example,<br />

when serial channel 1 completes a reception, it pulses both the interrupt request signal and<br />

the DMA request signal high for one clock cycle.<br />

Servicing the serial ports with DMA transfers (instead of interrupt requests) provides a tremendous<br />

gain in system throughput when blocks of serial data are transmitted and received. When<br />

using DMA-driven serial port transfers, it is important to note that as the baud rate of the transfer<br />

is increased, so does bus utilization by the DMA Unit. Using high baud rates or multiple channels<br />

can degrade CPU performance. (See “DMA-Driven Serial Transfers” on page 10-34.)<br />

10.1.5.4 Unsynchronized Transfers<br />

DMA transfers can be initiated directly by the system software by selecting unsynchronized<br />

transfers. Unsynchronized transfers continue, back-to-back, at the full bus bandwidth, until the<br />

channel’s transfer count reaches zero or DMA transfers are suspended by an NMI.<br />

10.1.6 DMA Transfer Counts<br />

Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total<br />

number of transfers the channel runs. The transfer count is decremented by one after each transfer<br />

(regardless of data size). The DMA channel can be programmed to terminate transfers when the<br />

transfer count reaches zero (also referred to as terminal count).<br />

10.1.7 Termination and Suspension of DMA Transfers<br />

When DMA transfers for a channel are terminated, no further DMA requests for that channel will<br />

be granted until the channel is re-started by direct programming. A suspended DMA transfer temporarily<br />

disables transfers in order to perform a specific task. A suspended DMA channel does<br />

not need to be re-started by direct programming.<br />

10-7

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