80C186EC/80C188EC Microprocessor User's Manual

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WATCHDOG TIMER UNIT Register Name: Register Mnemonic: Register Function: Watchdog Timer Reload Value (High) WDTRLDH Contains the upper 16 bits of the Watchdog Timer Reload Value. 15 0 W R 3 1 W R 3 0 W R 2 9 W R 2 8 W R 2 7 W R 2 6 W R 2 5 W R 2 4 W R 2 3 W R 2 2 W R 2 1 W R 2 0 W R 1 9 W R 1 8 W R 1 7 W R 1 6 A1308-0A Bit Mnemonic Bit Name Reset State Function WR31:16 Watchdog Timer Reload Value 0000H WR31:16 are the high-order bits of the Watchdog Timer Reload Value. Figure 12-5. WDT Reload Value (High) 12-9
WATCHDOG TIMER UNIT Register Name: Register Mnemonic: Register Function: Watchdog Timer Reload Value (Low) WDTRLDL Contains the lower 16 bits of the Watchdog Timer Reload Value. 15 0 W R 1 5 W R 1 4 W R 1 3 W R 1 2 W R 1 1 W R 1 0 W R 9 W R 8 W R 7 W R 6 W R 5 W R 4 W R 3 W R 2 W R 1 W R 0 A1309-0A Bit Mnemonic Bit Name Reset State Function WR15:0 Watchdog Timer Reload Value FFFFH WR15:0 are the low-order bits of the Watchdog Timer Reload Value. Figure 12-6. WDT Reload Value (Low) 12-10
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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Page 324 and 325: DIRECT MEMORY ACCESS UNIT XOR AX, A
Page 326 and 327: DIRECT MEMORY ACCESS UNIT $mod186 n
Page 328: Serial Communications Unit 11
Page 331 and 332: SERIAL COMMUNICATIONS UNIT 1 2 3 4
Page 333 and 334: SERIAL COMMUNICATIONS UNIT The RX m
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Page 339 and 340: SERIAL COMMUNICATIONS UNIT Register
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Page 347 and 348: SERIAL COMMUNICATIONS UNIT 11.2.3 P
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Page 351 and 352: SERIAL COMMUNICATIONS UNIT $mod186
Page 353 and 354: SERIAL COMMUNICATIONS UNIT mov dx,
Page 357 and 358: SERIAL COMMUNICATIONS UNIT mov dx,
Page 359 and 360: SERIAL COMMUNICATIONS UNIT Disconne
Page 364 and 365: CHAPTER 12 WATCHDOG TIMER UNIT Syst
Page 366 and 367: WATCHDOG TIMER UNIT Figure 12-3(b)
Page 368 and 369: WATCHDOG TIMER UNIT wdt_data segmen
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Page 374 and 375: WATCHDOG TIMER UNIT Register Name:
Page 376: WATCHDOG TIMER UNIT wdt_data segmen
Page 380 and 381: CHAPTER 13 INPUT/OUTPUT PORTS Many
Page 382 and 383: INPUT/OUTPUT PORTS 13.1.2 Output Po
Page 384 and 385: INPUT/OUTPUT PORTS From Port Direct
Page 386 and 387: INPUT/OUTPUT PORTS 13.1.4.3 Port 3
Page 388 and 389: INPUT/OUTPUT PORTS Register Name: R
Page 390 and 391: INPUT/OUTPUT PORTS Register Name: R
Page 392: Math Coprocessing 14
Page 395 and 396: MATH COPROCESSING 14.3 THE 80C187 M
Page 397 and 398: MATH COPROCESSING Available data ty
Page 399 and 400: MATH COPROCESSING 14.3.1.5 Constant
Page 401 and 402: MATH COPROCESSING Increasing Signif
Page 403 and 404: MATH COPROCESSING 14.4.1 Clocking t
Page 405 and 406: MATH COPROCESSING External Oscillat
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Page 409 and 410: MATH COPROCESSING $mod186 $modc187
Page 412: CHAPTER 15 ONCE MODE ONCE (pronounc
Page 416 and 417: APPENDIX A 80C186 INSTRUCTION SET A
Page 418 and 419: 80C186 INSTRUCTION SET ADDITIONS AN
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80C186 INSTRUCTION SET ADDITIONS AN
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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