80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
Register Name:
Register Mnemonic:
Register Function:
DMA Control Register
DxCON
Controls DMA channel parameters.
15 0
D
M
E
M
D
D
E
C
D
I
N
C
S
M
E
M
S
D
E
C
S
I
N
C
T
C
I
N
T
S
Y
N
1
S
Y
N
0
P
I
D
R
Q
C
H
G
S
T
R
T
W
O
R
D
A1180-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
TC
Terminal
Count
X
Set TC to terminate transfers on Terminal Count. This
bit is ignored for unsynchronized transfers (that is, the
DMA channel behaves as if TC is set, regardless of its
condition).
INT Interrupt X Set INT to generate an interrupt request on Terminal
Count. The TC bit must be set to generate an interrupt.
SYN1:0
Synchronization
Type
XX
Selects channel synchronization:
SYN1 SYN0 Synchronization Type
0 0 Unsynchronized
0 1 Source-synchronized
1 0 Destination-synchronized
1 1 Reserved (do not use)
P
Relative
Priority
X
Set P to select high priority for the channel; clear P to
select low priority for the channel.
IDRQ
Internal
DMA
Request
Select
X
Set IDRQ to select internal DMA requests and ignore
the external DRQ pin. Clear IDRQ to select the DRQ pin
as the source of DMA requests. When IDRQ is set, the
channel must be configured for source-synchronized
transfers (SYN1:0 = 01).
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Figure 10-13. DMA Control Register (Continued)
10-21