80C186EC/80C188EC Microprocessor User's Manual

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INDEX SCU asynchronous mode, 11-21–11-22 SCU master/slave network, 11-24– 11-32 initialization code, 11-26–11-28 _select_slave routine, 11-27–11-28 _send_slave_command routine, 11-32 _slave_1 routine, 11-29–11-31 SCU synchronous mode, 11-23 square-wave generator, 9-17–9-22 TCU configurations, 9-17–9-23 timed DMA transfers, 10-30–10-38 using the Poll command, 8-51 WDT disable, 12-7, 12-8 WDT initialization, 12-13 WDT reload sequence, 12-4, 12-5 data types, 2-37, 2-38 dynamic code relocation, 2-13, 2-14 interrupts, 2-44 overview, 2-17 See also Addressing modes, Instruction set Special fully nested mode, 8-19 Special mask mode, 8-19, 8-34–8-35 selecting, 8-35 SPICP0, 8-21, 8-24, 8-32, 8-34 SPICP1, 8-21, 8-25, 8-28, 8-29, 8-31 Square-wave generator, code example, 9-17–9-22 SS register, 2-1, 2-5, 2-6, 2-13, 2-15, 2-30, 2-45 Stack frame pointers, A-2 Stack Pointer, 2-1, 2-5, 2-13, 2-15, 2-45 Stack segment, 2-5 Stacks, 2-15 START registers, CSU, 6-5, 6-7, 6-11 STOP registers, CSU, 6-5, 6-8, 6-12 String instructions, 2-22–2-23 and addressing modes, 2-34 and memory-mapped I/O ports, 2-36 operand locations, 2-13 operands, 2-36 Strings accessing, 2-13, 2-34 defined, 2-37 Synchronizing asynchronous inputs, B-1 T Technical support, 1-6 Temporary real, defined, 14-7 Terminology "above" vs. "greater", 2-26 "below" vs. "less", 2-26 device names, 1-2 Timer Control Registers (TxCON), 9-7, 9-8 Timer Count Registers (TxCNT), 9-10 Timer Counter Unit (TCU), 9-1–9-23 and Power-Save mode, 5-20 application examples, 9-17–9-23 block diagram, 9-2 clock sources, 9-12 configuring a digital one-shot, 9-17–9-23 configuring a real-time clock, 9-17–9-19 configuring a square-wave generator, 9-17– 9-22 counting sequence, 9-12–9-13 dual maxcount mode, 9-13–9-14 enabling and disabling counters, 9-15–9-16 frequency, maximum, 9-17 initializing, 9-11 input synchronization, 9-17 Interrupt Request Latch Register (TIMIRL), 8-42 interrupts, 9-16 overview, 9-1–9-6 programming, 9-6–9-16 considerations, 9-16 pulsed output, 9-14–9-15 retriggering, 9-13–9-14 setup and hold times, 9-16 single maxcount mode, 9-13, 9-14–9-16 timer delay, 9-1 timing, 9-1 and BIU, 9-1 considerations, 9-16 TxOUT signal, 9-15 variable duty cycle output, 9-14–9-15 Timer Maxcount Compare Registers (TxCMPA, TxCMPB), 9-11 Timers‚ See Timer Counter Unit (TCU), Watchdog Timer Unit Training, 7 Index-9
INDEX Trap exceptions, 2-42 Trap Flag (TF), 2-7, 2-9, 2-43, 2-48 T-state and bus cycles, 3-9 and CLKOUT, 3-8 defined, 3-7 W Wait states and bus cycles, 3-13 and chip-selects, 6-11–6-14 and DRAM controllers, 7-1 and external 82C59A device, 8-46 and ICU, 8-44 and PCB accesses, 4-4 and READY input, 3-13 Watchdog Timer (WDT) Unit, 12-1–12-13 and Interrupt Control Unit, 12-2 block diagram, 12-2 disabling, 12-6–12-8 down counter, reloading, 12-1, 12-3, 12-4 generating interrupts, 12-3 initializing, 12-5 output waveforms, 12-6 overview, 12-1–12-2 registers, 12-8–12-13 reset circuit, 12-2 using as general-purpose timer, 12-6 using as watchdog, 12-1–12-5 WDT Count Value Register, 12-11, 12-12 WDT Reload Value Register, 12-9, 12-10 Word integer, defined, 14-7 World Wide Web, 1-6 Write bus cycle, 3-23 Z Zero Flag (ZF), 2-7, 2-9, 2-23 Index-10
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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Page 482 and 483: APPENDIX D INSTRUCTION SET OPCODES
Page 484 and 485: INSTRUCTION SET OPCODES AND CLOCK C
Page 504: Index
Page 507 and 508: INDEX AH register, 2-5 AL register,
Page 509 and 510: INDEX synchronization, 10-23 transf
Page 511 and 512: INDEX NMI, 2-42 generating with WDT
Page 513: INDEX bus latency, 7-7 calculating
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80C186EC/80C188EC Microprocessor User's Manual

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