80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
Non-Alike Access Recovery Time (T CHCL ) refers to the recovery time required by the 82C59A-2
between accesses of different types (e.g., a RD followed by a WR or a WR followed by an INTA).
This problem is more complicated than the back-to-back read or write recovery time because the
programmer does not typically have control over the INTA signal. The only way to avoid violating
this specification for INTA is to disable interrupts during reads or writes to the 82C59A-2 and
re-enable interrupts only after recovery time has elapsed. The “JMP $+2” method may be used
for wait states between reads and writes.
8.7 MODULE EXAMPLES
Example 8.1 is a template for system initialization. Follow this template closely when designing
your system software. Failure to initialize the 8259A modules correctly will result in system failure
and potential system damage.
Example 8.2 shows the code necessary to issue an End-of-Interrupt (EOI) command. Note the
clearing of the Interrupt Request Register bit to prevent unrequested interrupts from occurring.
Example 8.3 illustrates the use of the Poll command in lieu of normal interrupt servicing.
MOD186
NAME 80C186EC_ICU_INITIALIZATION_TEMPLATE
;The following code would typically be found in the boot section
;of the system software.
;It is assumed that the equates for the pcb register mnemonics
;are in the include file “pcb_equates.inc”
$INCLUDE (PCB_EQUATES.INC)
BOOT_ROM SEGMENT ;This is the boot rom code
ASSUME CS:BOOT_ROM, DS:NOTHING
;First, ensure that all external interrupts are disabled.
CLI
;Clear CPU interrupt enable
;Set up interrupt vector table. We only show the initialization of the timer 0
;vector. The timer 0 vector type is set to 28h (Type 40) in the slave 8259a
;initialization.
;Your system code needs to initialize all vectors for the 8259a modules and
;all exceptions and traps.
Example 8-1. Initializing the Interrupt Control Unit
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