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80C186EC/80C188EC Microprocessor User's Manual

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TIMER/COUNTER UNIT<br />

9.2.2 Clock Sources<br />

The 16-bit Timer Count register increments once for each timer event. A timer event can be a<br />

low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU<br />

clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 16 ) events can be counted.<br />

Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer<br />

events by setting the External (EXT) bit in their control registers. Transitions on the external pin<br />

are synchronized to the CPU clock before being presented to the timer circuitry. The timer counts<br />

transitions on this pin. The input signal must go low, then high, to cause the timer to increment.<br />

The maximum count-rate for the timers is ¼ the CPU clock rate (measured at CLKOUT) because<br />

the timers are serviced only once every four clocks.<br />

All timers can use transitions of the CPU clock as timer events. For internal clocking, the timer<br />

increments every fourth CPU clock due to the counter element’s time-multiplexed servicing<br />

scheme. Timer 2 can use only the internal clock as a timer event.<br />

Timers 0 and 1 can also use Timer 2 reaching its maximum count as a timer event. In this configuration,<br />

Timer 0 or Timer 1 increments each time Timer 2 reaches its maximum count. See Table<br />

9-1 for a summary of clock sources for Timers 0 and 1. Timer 2 must be initialized and running<br />

in order to increment values in other timer/counters.<br />

Table 9-1. Timer 0 and 1 Clock Sources<br />

EXT P Clock Source<br />

0 0 Timer clocked internally at ¼ CLKOUT frequency.<br />

0 1 Timer clocked internally, prescaled by Timer 2.<br />

1 X Timer clocked externally at up to ¼ CLKOUT frequency.<br />

9.2.3 Counting Modes<br />

All timers have a Timer Count register and a Maxcount Compare A register. Timers 0 and 1 also<br />

have access to a second Maxcount Compare B register. Whenever the contents of the Timer<br />

Count register equal the contents of the Maxcount Compare register, the count register resets to<br />

zero. The maximum count value will never be stored in the count register. This is because the<br />

counter element increments, compares and resets a timer in one clock cycle. Therefore, the maximum<br />

value is never written back to the count register. The Maxcount Compare register can be<br />

written at any time during timer operation.<br />

9-12

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