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80C186EC/80C188EC Microprocessor User's Manual

80C186EC/80C188EC Microprocessor User's Manual

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CLOCK GENERATION AND POWER MANAGEMENT<br />

Any unmasked interrupt received by the core will return the processor to Active mode. Interrupt<br />

requests pass through the Interrupt Control Unit with an interrupt resolution time for mask and<br />

priority level checking. Then, after 1½ clocks, the core clock begins toggling. It takes an additional<br />

6 CLKOUT cycles for the core to begin the interrupt vectoring sequence.<br />

After execution of the IRET (interrupt return) instruction in the interrupt service routine, the<br />

CS:IP will point to the instruction following the HALT. Interrupt execution does not modify the<br />

Power Control Register. Unless the programmer intentionally reprograms the register after exiting<br />

Idle mode, the processor will re-enter Idle mode at the next HLT instruction.<br />

Like an unmasked interrupt, an NMI will return the core to Active mode from Idle mode. It takes<br />

two CLKOUT cycles to restart the core clock after an NMI occurs. The NMI signal does not need<br />

the mask and priority checks that a maskable interrupt does. This results in a considerable difference<br />

in clock restart time between an NMI and an unmasked interrupt. The core begins the interrupt<br />

response six cycles after the core clock restarts when it fetches the NMI vector from location<br />

00008H. NMI does not clear the IDLE bit in the Power Control Register.<br />

Resetting the microprocessor will return the device to Active mode. Unlike interrupts, a reset<br />

clears the Power Control Register. Execution begins as it would following a warm reset (see “Reset<br />

and Clock Synchronization” on page 5-6).<br />

5.2.1.4 Example Idle Mode Initialization Code<br />

Example 5-1 illustrates programming the Power Control Register and entering Idle mode upon<br />

HLT. The interrupts from the serial port and timers are not masked. Assume that the serial port<br />

connects to a keyboard controller. At every keystroke, the keyboard sends a data byte, and the<br />

processor wakes up to service the interrupt. After acting on the keystroke, the core will go back<br />

into Idle mode. The example excludes the actual keystroke processing.<br />

5-15

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