80C186EC/80C188EC Microprocessor User's Manual

SERIAL COMMUNICATIONS UNIT
11.3.3.2 BCLK as Baud Timebase Clock
BCLK does not run directly into the baud timebase clock, but is first synchronized to the CPU
clock. BCLK causes the baud timebase clock to increment, but transitions on TXD and RXD (for
transmissions) still occur relative to CLKOUT.
A low-to-high transition on BCLK increments BxCNT. If BxCNT is equal to BxCMP, TXD goes
low approximately 4½ CLKOUTs later. TXD will always remain low for two CLKOUT periods
and then go high. TXD will go low again 4½ CLKOUTs after BxCNT equals BxCMP. Therefore,
the output frequency on TXD is roughly equal to the input frequency on BCLK multiplied by Bx-
CMP. There will be some clock jitter, as the output on TXD will always be some multiple of
CLKOUTs. This is due to the internal synchronization.
11.4 SERIAL COMMUNICATIONS UNIT INTERRUPTS
Serial communication is usually interrupt-driven. An interrupt needs to occur on each reception
and on each transmission of a character. The RI and TI flags in the SxSTS register (Figure 11-14
on page 11-16) provide the interrupt mechanism for the serial ports. The two serial ports, or channels,
have different interrupt circuitry. Serial channel 0 is directly supported by the integrated Interrupt
Control Unit. Serial channel 1 is supported by the RXI1 and TXI1 outputs. RXI1 and TXI1
go active during the stop bit of receive and transmit sequences, respectively. These outputs can
be connected to external interrupt pins. .
11.5 SERIAL PORT EXAMPLES
This section contains examples that show ways to use the serial port.
NOTE
The examples assume that the Peripheral Control Block is located in I/O space.
11.5.1 Asynchronous Mode Example
Example 11-1 contains sample code to initialize Serial Port 0 for 9600-baud operation in asynchronous
Mode 4.
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