80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
10.2.1.8 Setting the Relative Priority of a Channel
The priority of a channel within a module is controlled by the Priority bit in the DMA Control
Register (Figure 10-13 on page 10-20). A channel may be assigned either high or low priority. If
both channels are programmed to the same priority (i.e., both high or both low), the channels rotate
priority.
10.2.2 Setting the Inter-Module Priority
The inter-module priority for the DMA Unit is controlled by the DMAPA and DMAPB bits in
the DMA Module Priority Register (Figure 10-14 on page 10-24). A module may be assigned either
high or low priority. When both modules are assigned the same priority, the modules rotate
priority.
10.2.3 Using the DMA Unit with the Serial Ports
The following setup is used for DMA-serviced serial port reception.
• The source pointer points at the receive buffer (SxRBUF) in the serial port.
• The destination pointer points to the area in memory where the message will be saved.
• The DMA channel is programmed for serial channel requests.
• The transfer count register holds the length of the memory buffer.
The serial port DMA request pulses high after each byte is received. The DMA unit then fetches
the received byte from the receive buffer (SxRBUF) register and deposits it in memory. Typically,
the channel is programmed to interrupt the CPU when the memory buffer is full (i.e., when
the transfer count reaches zero).
The following setup is used for DMA-serviced serial port transmission.
• The source pointer points to the area of memory where the message resides.
• The destination pointer points to the transmit buffer (SxTBUF) for the serial channel.
• The DMA channel is programmed for serial channel requests.
• The transfer count register holds the length of the memory buffer.
The serial port DMA request pulses high after each byte is transmitted. The DMA unit then fetches
the next byte of the message from memory and deposits it in the transmit buffer (initiating another
transfer). Typically, the channel is programmed to interrupt the CPU when the memory
buffer is empty (i.e., when the transfer count reaches zero).
DMA-driven transmissions must be “primed” by sending the first byte manually, thus generating
the first transmit interrupt.
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