80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle continues
to float the bus. An idle bus state following a bus write cycle continues to drive the bus.
The BIU drives no control strobes active in an idle state except to indicate the start of another bus
cycle.
3.5 BUS CYCLES
There are four basic types of bus cycles: read, write, interrupt acknowledge and halt. Interrupt
acknowledge and halt bus cycles define special bus operations and require separate discussions.
Read bus cycles include memory, I/O and instruction prefetch bus operations. Write bus cycles
include memory and I/O bus operations. All read and write bus cycles have the same basic format.
The following sections present timing equations containing symbols found in the data sheet. The
timing equations provide information necessary to start a worst-case design analysis.
3.5.1 Read Bus Cycles
Figure 3-19 illustrates a typical read cycle. Table 3-2 lists the three types of read bus cycles.
Table 3-2. Read Bus Cycle Types
Status Bit
S2 S1 S0
Bus Cycle Type
0 0 1 Read I/O — Initiated by the Execution Unit for IN, OUT, INS, OUTS instructions
or by the DMA Unit. A19:16 are driven to zero (see Chapter 10, “Direct Memory
Access Unit”).
1 0 0 Instruction Prefetch — Initiated by the BIU. Data read from the bus fills the
prefetch queue.
1 0 1 Read Memory — Initiated by the Execution Unit, the DMA Unit or the Refresh
Control Unit. A19:0 select the desired byte or word memory location.
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