80C186EC/80C188EC Microprocessor User's Manual

CLOCK GENERATION AND POWER MANAGEMENT
If the processor needs to run a refresh cycle during Idle mode, the internal core clock begins to
toggle on the falling CLKOUT edge immediately after the down-counter reaches zero. After one
idle T-state, the processor runs the refresh cycle. As with all other bus cycles, the BIU uses the
ready, wait state generation and chip-select circuitry as necessary for refresh cycles during Idle
mode. There is one idle T-state after T4 before the internal core clock shuts off again.
A HOLD request from an external bus master turns on the core clock as long as HOLD is active
(see Figure 5-11). The core clock restarts one CLKOUT cycle after the bus processor samples
HOLD high. The microprocessor asserts HLDA one cycle after the core clock starts. The core
clock turns off and the processor deasserts HLDA one cycle after the external bus master deasserts
HOLD.
1 Clock
Delay
Core
Restart
Processor
In Hold
Core Clock
Shuts Off
CLKOUT
Internal
Peripheral
Clock
Internal
Core Clock
HOLD
TI TI TI TI TI TI TI TI TI TI TI TI
HLDA
A1120-0A
Figure 5-11. HOLD/HLDA During Idle Mode
As in Active mode, refresh requests will force the BIU to drop HLDA during bus hold. (For more
information on refresh cycles during hold, see “Refresh Operation During a Bus HOLD” on page
3-43 and “Refresh Operation and Bus HOLD” on page 7-13.) Refresh requests will also correctly
break into sequences of back-to-back DMA cycles.
5.2.1.3 Leaving Idle Mode
Any unmasked interrupt or non-maskable interrupt (NMI) will return the processor to Active
mode. Reset also returns the processor to Active mode, but the device loses its prior state.
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