80C186EC/80C188EC Microprocessor User's Manual

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
The CPU is now executing the interrupt service routine. The programmer must save (usually by
pushing onto the stack) all registers used in the interrupt service routine; otherwise, their contents
will be lost. To allow nesting of maskable interrupts, the programmer must set the Interrupt Enable
bit in the Processor Status Word.
When exiting an interrupt service routine, the programmer must restore (usually by popping off
the stack) the saved registers and execute an IRET instruction, which performs the following
steps.
1. Loads the return CS and IP by popping them off the stack.
2. Pops and restores the old Processor Status Word from the stack.
The CPU now executes from the point at which the interrupt or exception occurred.
Stack
PSW
1
Interrupt Enable Bit
Trap Flag
2
CS
0 0
Processor Status Word
SP
IP
3
Code Segment Register
Instruction Pointer
4
CS
IP
Interrupt
Vector
Table
A1029-0A
Figure 2-26. Interrupt Sequence
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