80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.4.4 The Operation Command Words
The 8259A is reprogrammed during program execution by using the Operation Command
Words. The Operation Command Words can be sent at any time after initialization of the 8259A
module is complete. The three Operation Command Words (OCW1, OCW2 and OCW3) are addressed
through a combination of the A1 (register address) line and the state of data bits D3 and
D4 (see Table 8-1).
Table 8-1. Operation Command Word Addressing
Access Port Register A1 D4 D3
SPICP1 OCW1 1 X X
SPICP0 OCW2 0 0 0
SPICP0 OCW3 0 0 1
8.4.4.1 Masking Interrupts: OCW1
OCW1 (Figure 8-17) is the Interrupt Mask Register. Setting a bit in the Interrupt Mask Register
inhibits further interrupts from the corresponding IR line. For example, if the M3 bit is set, then
the IR3 line cannot generate interrupts. Clearing a bit in the Interrupt Mask Register enables interrupts
from the corresponding IR line.
Note that the Interrupt Mask Register operates on the output of the Interrupt Request Register.
The IR lines can still set the bits in the Interrupt Request Register, even though they are masked.
An interrupt will be requested if a masked IR line sets its Interrupt Request bit and then is unmasked.
The Interrupt Mask Register is read directly by read cycles with A1=1 (the MPICP1 and SPICP1
Peripheral Control Block registers).
8.4.4.2 EOI And Interrupt Priority: OCW2
OCW2 (Figure 8-18) is used to set priority and execute EOI commands. The R (rotate), SL (specific
level) and EOI (end-of-interrupt) bits comprise a three-bit instruction field. The instruction
field is decoded as shown in Table 8-2.
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