80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
8.4.3.3 ICW2: Base Interrupt Type
ICW2 (Figure 8-13) specifies the five most-significant bits of the interrupt type for the 8259A
module. The lower three bits are automatically set equal to the interrupt request line that is being
acknowledged. For example, if ICW2 is programmed to 20H (for a Type 32 interrupt) and IR4 is
being acknowledged, interrupt type 24H (for a Type 36 interrupt) is driven on the bus during an
interrupt acknowledge cycle.
Register Name: Initialization Command Word 2
Register Mnemonic: ICW2 (accessed through MPICP1 and SPICP1)
Register Function: Sets the base interrupt type for the module.
15 0
T
7
T
6
T
5
T
4
T
3
T
2
T
1
T
0
A1221-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
T7:3 Interrupt
Type
X
Write the five high-order bits of the base
address for the interrupt type (from the Interrupt
Vector Table, Figure 2-25 on page 2-40) to the
T7:3 bits. For example, write 20H to these bits
to specify a Type 8 interrupt.
T2:0 IR Line X T2:0 are automatically set equal to the interrupt
request line that is being acknowledged.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-13. ICW2 Register
NOTE
Pay strict attention to reserved interrupt types (see Figure 2-25 on page 2-40)
when assigning a base interrupt type to an 8259A module. Use of the reserved
interrupt types could cause incompatibilities with future Intel products.
8-25