80C186EC/80C188EC Microprocessor User's Manual

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CHAPTER 8 INTERRUPT CONTROL UNIT The Interrupt Control Unit (ICU) is composed of two 8259A modules connected in cascade and three Interrupt Request Latch Registers (Figure 8-1). The slave 8259A module controls seven internal interrupt sources and one external interrupt source (INT7). The master 8259A module controls seven external interrupt sources (INT6–INT0) and the slave module cascade request. The 8259A modules are hardwired for master and slave operation. The master 8259A module offers the ability to cascade to up to seven other 8259A modules. This arrangement is used to expand the interrupt handling capability of an <strong>80C186EC</strong>/C188EC system to 57 external sources. The 8259A modules make up the heart of the Interrupt Control Unit. These modules are full implementations of the industry standard 8259A architecture. Those readers already familiar with the 8259A may be tempted to skip the following sections. DO NOT. There are subtle, yet extremely important, differences between the discrete implementation of the 8259A and the integrated module. To understand the function of the Interrupt Control Unit, you must first understand the architecture and programming of a single 8259A module. The remainder of this chapter is organized as follows: • Functional overview of the interrupt controller • Interrupt priority and nesting • Architecture and programming of a single 8259A module • Integration of the 8259A modules into the Interrupt Control Unit • Programming of the Interrupt Control Unit • Hardware interfacing and examples 8.1 FUNCTIONAL OVERVIEW: THE INTERRUPT CONTROLLER All microcomputer systems must communicate in some way with the external world. A typical system might have a keyboard, a disk drive and a communications port, all requiring CPU attention at different times. There are two distinct ways to process peripheral I/O requests: polling and interrupts. 8-1
INTERRUPT CONTROL UNIT Master 8259A INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Internal Interrupt Request Latch Registers TMI0 TMI1 DMAI2 DMAI3 TMI2 RXI0 TXI0 INT7 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 CAS2 CAS1 CAS0 INT INTA D7:0 A0 Slave 8259A INT CAS2 CAS1 CAS0 INTA D7:0 A0 Internal Data Bus (F-Bus) A1 Internal Address Bus A1 Internal Control Bus CAS Bus Interrupt Requests From Integrated Peripherals A1217-0A Figure 8-1. Interrupt Control Unit Block Diagram 8-2
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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Page 159 and 160: CLOCK GENERATION AND POWER MANAGEME
Page 172 and 173: CHAPTER 6 CHIP-SELECT UNIT Every sy
Page 174 and 175: CHIP-SELECT UNIT Stop Value Ignore
Page 176 and 177: CHIP-SELECT UNIT Address 1 Ready Fl
Page 178 and 179: CHIP-SELECT UNIT Register Name: Reg
Page 180 and 181: CHIP-SELECT UNIT Register Name: Reg
Page 182 and 183: CHIP-SELECT UNIT In the previous eq
Page 184 and 185: CHIP-SELECT UNIT No Any READY = 1 W
Page 186 and 187: CHIP-SELECT UNIT The GCS chip-selec
Page 188 and 189: CHIP-SELECT UNIT $ TITLE (Chip-Sele
Page 190 and 191: CHIP-SELECT UNIT ;SET UP CHIP SELEC
Page 192: Refresh Control Unit 7
Page 195 and 196: REFRESH CONTROL UNIT 7.1 THE ROLE O
Page 197 and 198: REFRESH CONTROL UNIT The BIU does n
Page 199 and 200: REFRESH CONTROL UNIT CLKOUT T4 T1 T
Page 201 and 202: REFRESH CONTROL UNIT 7.7.2.1 Refres
Page 203 and 204: REFRESH CONTROL UNIT Register Name:
Page 205 and 206: REFRESH CONTROL UNIT $mod186 name e
Page 207 and 208: REFRESH CONTROL UNIT T1 T1 T1 T1 T1
Page 212 and 213: INTERRUPT CONTROL UNIT Polling requ
Page 214 and 215: INTERRUPT CONTROL UNIT INT INTA D7:
Page 216 and 217: INTERRUPT CONTROL UNIT Edge Sense L
Page 218 and 219: INTERRUPT CONTROL UNIT 8.3.2 Interr
Page 220 and 221: INTERRUPT CONTROL UNIT 8.3.3.1 Defa
Page 222 and 223: INTERRUPT CONTROL UNIT More than on
Page 224 and 225: INTERRUPT CONTROL UNIT IR0 IR1 IR2
Page 226 and 227: INTERRUPT CONTROL UNIT 10. On the s
Page 228 and 229: INTERRUPT CONTROL UNIT 8.3.7 Altern
Page 230 and 231: INTERRUPT CONTROL UNIT 8.4.2 Progra
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Page 236 and 237: INTERRUPT CONTROL UNIT Register Nam
Page 242 and 243: INTERRUPT CONTROL UNIT Table 8-2. O
Page 244 and 245: INTERRUPT CONTROL UNIT The ESMM (En
Page 246 and 247: INTERRUPT CONTROL UNIT Internal Int
Page 248 and 249: INTERRUPT CONTROL UNIT To Slave 825
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Page 254 and 255: INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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