80C186EC/80C188EC Microprocessor User's Manual

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INTERRUPT CONTROL UNIT CPU WR RD GCS D7:0 INTA INT6 From latched address line (Note) Master 8259A WR IR0 RD IR1 CS IR2 IR3 A0 IR4 IR5 IR6 D7:0 IR7 INTA SP/EN INT CAS2 CAS1 CAS0 AD15/CAS2 AD14/CAS1 AD13/CAS0 Note: Latched A0 is used for <strong>80C188EC</strong>, latched A1 is used for <strong>80C186EC</strong> A1238-0A Figure 8-29. Typical Cascade Connection for 82C59A-2 8.6.4.1 The External INTA Cycle Every interrupt acknowledge (INTA) cycle, including those that access the internal 8259A modules, is visible on the external processor pins. For an internal interrupt acknowledge, the interrupt type driven by the internal 8259A module does not appear on the external bus (and anything driven on the external bus is ignored). The AD15:13/CAS2:0 lines drive the slave address (if one) during both internal and external interrupt acknowledge cycles. The INTA cycle is described in greater detail in Chapter 3, “Bus Interface Unit.” 8-45
INTERRUPT CONTROL UNIT The AD15:13 pins are used for CAS2:0 information only during interrupt acknowledge cycles. There is no need to latch the AD15:13/CAS2:0 signals during interrupt acknowledge cycles; the 8259A family devices have internal CAS latches that are activated by the INTA signal. The 8259A family devices ignore the state of the CAS lines except during interrupt acknowledge cycles. The AD15:13/CAS2:0 lines begin driving the Slave ID as soon as it is available internally. 8.6.4.2 Timing Constraints There are several timing constraints to be aware of when connecting an external 8259 device. The following discussion is based on an analysis of the 82C59A-2 device specifications. The 82C59A-2 is the fastest 8259A family device currently available from Intel. Minimum RD/INTA Pulse Width (T RLRH ) can be met for read cycles by inserting wait states (with the Chip-Select Unit or an external wait state generator). Minimum INTA pulse width can be met for interrupt acknowledge cycles by inserting wait states as well. Minimum Write Pulse Width (T WLWH ) and Minimum Data Setup Time (T DVWH ) can be met by inserting wait states into write cycles to the 82C59A-2. Data Float After RD or INTA (T RHDZ ) can be guaranteed only below a processor frequency of 11.76 MHz. Above 11.76 MHz, the 82C59A-2 device (or devices) must be buffered with a transceiver (a 74F245 or the equivalent). Without the transceiver, the 82C59-A2 device does not stop driving the data bus in time for the next bus cycle, causing bus contention. Back-to-Back Reads (T RHRL ) and Back-to-Back Writes (T WHWL ) both refer to the recovery time required by the 82C59A-2 between two accesses of the same type. This recovery time specification is violated above a processor frequency of 12.5 MHz. The simplest way to solve this problem is to insert a “software wait state” in the programming code. The most common software wait state is the “JMP $+2” instruction. “JMP $+2” ensures an uninterruptable delay of 14 clock cycles. Figure 8-30 shows the use of the “JMP $+2” instruction in a typical programming sequence. MOV DX, EXT59_ODD;ACCESS IMR (A0=1) MOV AL, 07FH;UNMASK IR7 ONLY OUT DX, AL JMP $+2 ;SOFTWARE WAIT STATE MOV DX, EXT59_EVN ;READ ISR (A0=1, ISR ;WILL BE SELECTED) MOV AL, 0BH;READ ISR COMMAND OUT DX, AL Figure 8-30. Software Wait State for External 82C59A-2 8-46
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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Page 205 and 206: REFRESH CONTROL UNIT $mod186 name e
Page 207 and 208: REFRESH CONTROL UNIT T1 T1 T1 T1 T1
Page 210 and 211: CHAPTER 8 INTERRUPT CONTROL UNIT Th
Page 212 and 213: INTERRUPT CONTROL UNIT Polling requ
Page 214 and 215: INTERRUPT CONTROL UNIT INT INTA D7:
Page 216 and 217: INTERRUPT CONTROL UNIT Edge Sense L
Page 218 and 219: INTERRUPT CONTROL UNIT 8.3.2 Interr
Page 220 and 221: INTERRUPT CONTROL UNIT 8.3.3.1 Defa
Page 222 and 223: INTERRUPT CONTROL UNIT More than on
Page 224 and 225: INTERRUPT CONTROL UNIT IR0 IR1 IR2
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Page 228 and 229: INTERRUPT CONTROL UNIT 8.3.7 Altern
Page 230 and 231: INTERRUPT CONTROL UNIT 8.4.2 Progra
Page 232 and 233: INTERRUPT CONTROL UNIT Begin Initia
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Page 236 and 237: INTERRUPT CONTROL UNIT Register Nam
Page 242 and 243: INTERRUPT CONTROL UNIT Table 8-2. O
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Page 248 and 249: INTERRUPT CONTROL UNIT To Slave 825
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Page 266 and 267: TIMER/COUNTER UNIT Timer 0 Timer 1
Page 268 and 269: TIMER/COUNTER UNIT Continued From "
Page 270 and 271: TIMER/COUNTER UNIT Register Name: R
Page 276 and 277: TIMER/COUNTER UNIT The timer counti
Page 278 and 279: TIMER/COUNTER UNIT Timer 0 Serviced
Page 280 and 281: TIMER/COUNTER UNIT 9.3.2 Synchroniz
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Page 286: TIMER/COUNTER UNIT _CMPB equ word p
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Page 292 and 293: DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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