80C186EC/80C188EC Microprocessor User's Manual

INSTRUCTION SET DESCRIPTIONS
Table C-4. Instruction Set (Continued)
Name Description Operation
SUB
TEST
NOTE:
Subtract:
SUB dest, src
The source operand is subtracted from
the destination operand, and the result
replaces the destination operand. The
operands may be bytes or words. Both
operands may be signed or unsigned
binary numbers (see AAS and DAS).
Instruction Operands:
SUB reg, reg
SUB reg, mem
SUB mem, reg
SUB accum, immed
SUB reg, immed
SUB mem, immed
Test:
TEST dest, src
Performs the logical "and" of the two
operands (bytes or words), updates
the flags, but does not return the
result, i.e., neither operand is
changed. If a TEST instruction is
followed by a JNZ (jump if not zero)
instruction, the jump will be taken if
there are any corresponding one bits
in both operands.
Instruction Operands:
TEST reg, reg
TEST reg, mem
TEST accum, immed
TEST reg, immed
TEST mem, immed
(dest) ← (dest) – (src)
(dest) and (src)
(CF ) ← 0
(OF) ← 0
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
the contents of the flag is undefined after the instruction is executed
üthe flag is updated after the instruction is executed
Flags
Affected
AF ü
CF ü
DF –
IF –
OF ü
PF ü
SF ü
TF –
ZF ü
AF
CF ü
DF –
IF –
OF ü
PF ü
SF ü
TF –
ZF ü
C-45