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80C186EC/80C188EC Microprocessor User's Manual

80C186EC/80C188EC Microprocessor User's Manual

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TIMER/COUNTER UNIT<br />

Register Name:<br />

Register Mnemonic:<br />

Register Function:<br />

Timer Maxcount Compare Register<br />

T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA<br />

Contains timer maximum count value.<br />

15 0<br />

T<br />

C<br />

1<br />

5<br />

T<br />

C<br />

1<br />

4<br />

T<br />

C<br />

1<br />

3<br />

T<br />

C<br />

1<br />

2<br />

T<br />

C<br />

1<br />

1<br />

T<br />

C<br />

1<br />

0<br />

T<br />

C<br />

9<br />

T<br />

C<br />

8<br />

T<br />

C<br />

7<br />

T<br />

C<br />

6<br />

T<br />

C<br />

5<br />

T<br />

C<br />

4<br />

T<br />

C<br />

3<br />

T<br />

C<br />

2<br />

T<br />

C<br />

1<br />

T<br />

C<br />

0<br />

A1300-0A<br />

Bit<br />

Mnemonic<br />

Bit Name<br />

Reset<br />

State<br />

Function<br />

TC15:0<br />

Timer<br />

Compare<br />

Value<br />

XXXXH<br />

Contains the maximum value a timer will count<br />

to before resetting its Count register to zero.<br />

Figure 9-8. Timer Maxcount Compare Registers<br />

9.2.1 Initialization Sequence<br />

When initializing the Timer/Counter Unit, the following sequence is suggested:<br />

1. If timer interrupts will be used, program interrupt vectors into the Interrupt Vector Table.<br />

2. Clear the Timer Count register. This must be done before the timer is enabled because<br />

the count register is undefined at reset. Clearing the count register ensures that counting<br />

begins at zero.<br />

3. Write the desired maximum count value to the Timer Maxcount Compare register. For<br />

dual maximum count mode, write a value to both Maxcount Compare A and B.<br />

4. Program the Timer Control register to enable the timer. When using Timer 2 to prescale<br />

another timer, enable Timer 2 last. If Timer 2 is enabled first, it will be at an unknown<br />

point in its timing cycle when the timer to be prescaled is enabled. This results in an<br />

unpredictable duration of the first timing cycle for the prescaled timer.<br />

9-11

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