80C186EC/80C188EC Microprocessor User's Manual

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SERIAL COMMUNICATIONS UNIT 11.5.2 Mode 0 Example Example 11-2 shows a sample Mode 0 application. $mod186 name example_SCU_mode_0 ;************************************************************** ; FUNCTION: This function transmits the user's data, user_data, serially ; over RXD1. TXD1 provides the transmit clock. The transmission frequency ; is calculated as follows: ; ; tran_freq = (0.5*CLKIN/BAUDRATE)-1 ; ; A 0-1-0 pulse on P1.0 indicates the end of transmission. ; ; SYNTAX: extern void far parallel_serial(char user_data,int tran_freq) ; ; INPUTS: user_data - byte to send out serially ; tran_freq - baud rate compare value ; OUTPUTS: None ; NOTE: Parameters are passed on the stack as required by high-level ; languages. ;************************************************************** B1CMP equ xxxxH ;Channel 1 Baud Rate Compare S1CON equ xxxxH ;Channel 1 Control S1STS equ xxxxH ;Channel 1 Status S1TBUF equ xxxxH ;Channel 1 Receive Buffer ;xxxx - substitute register offset ;Example assumes that all the port pins are configured correctly and ;PCB is located in I/O space. lib_80186 segment public 'code' assume cs:lib_80186 public _parallel_serial _parallel_serialproc far push bp ;save caller's bp mov bp, sp ;get current top of stack user_data tran_freq equ word ptr [bp+6];get parameters off the stack equ word ptr [bp+8] push ax ;save registers that push dx ;will be modified mov dx, S1STS ;clear any pending exceptions Example 11-2. Mode 0 Example 11-23
SERIAL COMMUNICATIONS UNIT mov dx, P1CON ;Get state of port 1 controls in ax, dx and ax, 0feh ;make sure P1.0 is port out dx, al mov dx, B1CMP mov ax, tran_freq or ax, 8000h ;set internal clocking bit out dx, ax ;Mode 0, 1 million bps mov dx, P2CON ;set Port 2.1 for TXD mov ax, 0ffh out dx, al mov dx, S1TBUF ;send user's data mov ax, user_data out dx, al mov dx, S1CON ;Mode 0, No CTS, Transmit xor ax, ax out dx, ax mov dx, S1STS Check_4_TI: in ax, dx test ax, 0020h ;check for TI bit jz Check_4_TI _parallel_serial endp lib_80186 ends end mov dx, P1LTCH ;pulse P1.0 xor ax, ax out dx, al not ax ;set P1.0 high out dx, al not ax ;set P1.0 low out dx, al pop dx ;restore saved registers pop ax pop bp ;restore user's bp ret Example 11-2. Mode 0 Example (Continued) 11.5.3 Master/Slave Example This section shows an example of a Mode 2 and 3 master/slave network. Figure 11-18 shows the proper connection of the master to the slaves. The buffer is necessary to avoid contention on the receive line. Alternatively, an open-collector buffer could be used and the port pin function could be deleted. 11-24
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
Page 302 and 303: DIRECT MEMORY ACCESS UNIT 10.1.11.1
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Page 320 and 321: DIRECT MEMORY ACCESS UNIT $MOD186 n
Page 322 and 323: DIRECT MEMORY ACCESS UNIT SECTORS M
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Page 328: Serial Communications Unit 11
Page 331 and 332: SERIAL COMMUNICATIONS UNIT 1 2 3 4
Page 333 and 334: SERIAL COMMUNICATIONS UNIT The RX m
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Page 345 and 346: SERIAL COMMUNICATIONS UNIT The seri
Page 347 and 348: SERIAL COMMUNICATIONS UNIT 11.2.3 P
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Page 351: SERIAL COMMUNICATIONS UNIT $mod186
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Page 357 and 358: SERIAL COMMUNICATIONS UNIT mov dx,
Page 359 and 360: SERIAL COMMUNICATIONS UNIT Disconne
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Page 364 and 365: CHAPTER 12 WATCHDOG TIMER UNIT Syst
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Page 386 and 387: INPUT/OUTPUT PORTS 13.1.4.3 Port 3
Page 388 and 389: INPUT/OUTPUT PORTS Register Name: R
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Page 392: Math Coprocessing 14
Page 395 and 396: MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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