80C186EC/80C188EC Microprocessor User's Manual

WATCHDOG TIMER UNIT
wdt_data
segment
wdt_key DB 0AAH, 055H
wdt_data
ends
pcb_image segment ;image of PCB
WDTCLR EQU XXXXH ;replace “XXXX” with appropriate
;offset from PCB+0.
WDTCLR DW
pcb_image
wdt_code
ends
segment
assume cs:wdt_code
mov ax, seg wdt_key
mov ds, ax
mov si, offset wdt_key
;DS:SI = address of WDT reset value
mov ax, seg WDTCLR
mov es, ax
mov di, offset WDTCLR
;ES:DI = address of WDTCLR register
cld
;clear direction flag (autoincrement)
mov cx, 2 ;2 bytes in key
lock rep movsb ;LOCKed reload sequence
;The WDT down counter
;has been reloaded.
wdt_code ends
Example 12-2. Reload Sequence (Peripheral Control Block Located in Memory Space)
12.2.3 Initialization
The Watchdog Timer Unit is enabled following a reset. The initial value in the down counter is
0FFFFH. The system software must program or reload the Watchdog Timer within 65,535 clock
cycles of a reset to prevent the WDTOUT signal from being asserted.
Use the following sequence to initialize the Watchdog Timer:
1. Program the upper 16 bits of the WDT Reload Value (in the WDTRLDH register).
2. Program the lower 16 bits of the WDT Reload Value (in the WDTRLDL register).
3. Execute the appropriate LOCKed instruction sequence to reload the down counter and
lock accesses to the WDT Reload Value.
12-5