80C186EC/80C188EC Microprocessor User's Manual

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Index Double Index BX BX SI or or or Encoded in the Instruction BP or SI or BP + DI EU DI Explicit in the Instruction + Displacement + Effective Address CS 0000 or Assumed Unless Overridden by Prefix SS 0000 or DS 0000 BIU or + ES 0000 + Physical Addr A1015-0A Figure 2-12. Memory Address Computation The displacement is an 8- or 16-bit number contained in the instruction. The displacement generally is derived from the position of the operand’s name (a variable or label) in the program. The programmer can modify this value or explicitly specify the displacement. 2-29
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The BX or BP register can be specified as the base register for an effective address calculation. Similarly, either the SI or the DI register can be specified as the index register. The displacement value is a constant. The contents of the base and index registers can change during execution. This allows one instruction to access different memory locations depending upon the current values in the base or base and index registers. The default base register for effective address calculations with the BP register is SS, although DS or ES can be specified. Direct addressing is the simplest memory addressing mode (see Figure 2-13). No registers are involved, and the effective address is taken directly from the displacement of the instruction. Programmers typically use direct addressing to access scalar variables. With register indirect addressing, the effective address of a memory operand can be taken directly from one of the base or index registers (see Figure 2-14). One instruction can operate on various memory locations if the base or index register is updated accordingly. Any 16-bit general register can be used for register indirect addressing with the JMP or CALL instructions. In based addressing, the effective address is the sum of a displacement value and the contents of the BX or BP register (see Figure 2-15). Specifying the BP register as a base register directs the Bus Interface Unit to obtain the operand from the current stack segment (unless a segment override prefix is present). This makes based addressing with the BP register a convenient way to access stack data. Opcode Mod R/M Displacement EA A1016-0A Figure 2-13. Direct Addressing 2-30
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
Page 11 and 12: CONTENTS 11.4 SERIAL COMMUNICATIONS
Page 13 and 14: CONTENTS FIGURES Figure Page 2-1 Si
Page 15 and 16: CONTENTS FIGURES Figure Page 6-6 ST
Page 17 and 18: CONTENTS FIGURES Figure Page 11-18
Page 19 and 20: CONTENTS Table TABLES Page C-1 Inst
Page 22: Introduction 1
Page 25 and 26: INTRODUCTION The 80C186 Modular Cor
Page 27 and 28: INTRODUCTION Table 1-2. Related Doc
Page 29 and 30: INTRODUCTION 1.3.2.1 How to Find Ap
Page 32: Overview of the 80C186 Family Archi
Page 35 and 36: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 61: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 84: Bus Interface Unit 3
Page 87 and 88: BUS INTERFACE UNIT Physical Impleme
Page 89 and 90: BUS INTERFACE UNIT (X + 1) (X) A19:
Page 91 and 92: BUS INTERFACE UNIT For word transfe
Page 93 and 94: BUS INTERFACE UNIT CLKOUT T4 T1 T2
Page 95 and 96: BUS INTERFACE UNIT CLKOUT T4 or TI
Page 97 and 98: BUS INTERFACE UNIT Signals From CPU
Page 99 and 100: BUS INTERFACE UNIT T2 T3 or TW T4 o
Page 101 and 102: BUS INTERFACE UNIT A normally not-r
Page 103 and 104: BUS INTERFACE UNIT T2 or T3 or TW T
Page 105 and 106: BUS INTERFACE UNIT An idle bus stat
Page 107 and 108: BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
Page 109 and 110: BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
Page 111 and 112: BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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