80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
+5
+5
PRE
D Q Latched HLDA
HLDA
CLR
RESOUT
HOLD
A1310-0A
Figure 3-36. Latching HLDA
The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain
the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is
complete, the BIU will release the bus and generate HLDA.
3.7.2 Exiting HOLD
Figure 3-37 shows the timing associated with exiting the bus hold state. Normally a bus operation
(e.g., an instruction prefetch) occurs just after HOLD is released. However, if no bus cycle is
pending when leaving a bus hold state, the bus and associated control signals remain floating, if
the system is in normal operating mode. (For signal states associated with Idle and Powerdown
modes, see “Temporarily Exiting the HALT Bus State” on page 3-32).
3-45