80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
Fetch Cycle
Deposit Cycle
T1 T2 T3 T4
T1 T2 T3 T4
TI
TI
CLKOUT
DRQ
(Case 1)
1
DRQ
(Case 2)
2
NOTES:
1. Current destination synchronized transfer will not be immediately
followed by another DMA transfer.
2. Current destination synchronized transfer will be immediately
followed by another DMA transfer.
A1189-0A
Figure 10-4. Destination-Synchronized Transfers
10.1.5 Internal Requests
Internal DMA requests can come from either an integrated peripheral or the system software.
10.1.5.1 Integrated Peripheral Requests
All four channels can be programmed to accept internal DMA requests from either Timer 2 or the
Serial Communications Unit. The request signals from the Serial Communications Unit and Timer
2 connect to the DMA unit through the Internal DMA Request Multiplexer. (See “The Internal
DMA Request Multiplexer” on page 10-11.)
10.1.5.2 Timer 2-Initiated Transfers
When programmed for Timer 2-initiated transfers, the DMA channel performs one DMA transfer
every time that Timer 2 reaches its maximum count. Timer-initiated transfers are useful for servicing
time-based peripherals. For example, an A/D converter would require data every 22 microseconds
in order to produce an audio range waveform. In this case, the DMA source would
point to the waveform data, the destination would point to the A/D converter and Timer 2 would
request a transfer every 22 microseconds. (See “Timed DMA Transfers” on page 10-37.)
10-6