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etude theorique et experimentale du transport electronique ... - Ief

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Chapitre IV : Modélisation analytique <strong>du</strong> <strong>transport</strong> quasi balistique[48] “Stress modelling of Nano-scale MOSFET” N Shah, Université de Floride, 2005, Disponiblesur: http://www.swamp.tec.ufl.e<strong>du</strong>/images/shah_n.pdf[49] “Etudes théoriques de structures pour l’électronique rapide <strong>et</strong> contribution au développementd’un simulateur particulaire Monte Carlo”, P. Dollfus, Habilitation à diriger les recherches,n°363, 1999.[50] “Band offs<strong>et</strong> in<strong>du</strong>ced threshold variation in strained-Si nMOSFETs”, J.-S. Goo, Q. Xiang, Y.Takamura, F. Arasnia, E.N. Paton, P. Besser, J. Pan, M-R Lin, Electron Device L<strong>et</strong>ters, IEEE,vol. 24, issue 9, 2003, pp: 568-570.[51] “Control of threshold voltage and short channel effects in ultra-thin strained-SOI CMOS”T. Numata, T. Mizuno, T. Tezuka, J. Koga, S. Takagi, SOI Conference, 2003. IEEEInternational, 29 Sept.-2 Oct. 2003, pp: 119 - 121[52] “Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator(SGOI) substrates”, Z-Y Cheng, M.T Currie, C.W. Leitz, G. Taraschi, E.A. Fitzgerald, J.L.Hoyt, D.A. Antoniadas, Electron Device L<strong>et</strong>ters, IEEE, vol. 22, issue 7, 2001, pp:321 – 323.[53] “Formation à Visual C++ 6.0”, Chuck Sphar, Microsoft Press, 2000.- 186 -

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